Make sure the next Card you purchase has... BUS-65153 MIL-STD-1553B, NOTICE 2 AND MIL-STD-1760B SMALL TERMINAL INTERFACE CIRCUIT "STIC" (R) FEATURES * Supports MIL-STD-1553B Notice 2 and MIL-STD-1760 Stores Management * Complete Intergrated Remote Terminal Including: *Dual Low-Power Transceiver *Complete RT Protocol Logic * Small, 70-Pin Ceramic Package * Choice of 5V or 3.3V Logic Power * Meets 1553A/McAir Response Time Requirements * Selectable 8/16-bit DMA Interface DESCRIPTION * Optional Tri-State Address Bus and Transfer Control Signals The BUS-65153 is a complete, dual redundant MIL-STD-1553B Remote Terminal. Packaged in a 1.9" x 1.0" x 0.2", 70-pin ceramic package, the BUS-65153 provides the transmitter voltage level required by MIL-STD-1760. Also in support of MIL-STD-1760, the RT address inputs are latchable. * Direct Interface to Simple Systems * Selectable Input Clock, 12 or 16 MHz * MIL-PRF-38535 Processing Available The BUS-65153 contains two low power transceivers and a DDC custom designed chip. This chip includes dual encoder/decoder, RT protocol logic, tristate data buffers, and DMA transfer control logic.The BUS-65153 supports all 13 dual redundant mode codes, any combination of which may be illegalized by an external PROM, PLD, or RAM device. Parallel data transfers are accomplished via a DMA type interface. Both 8-bit and 16-bit transfers are supported. The BUS-65153 can be easily interfaced to most CPU's. In addition, the BUS-65153 can interface directly to minimum complexity subsystems such as switches, D/A converters, etc. The address bus and transfer control signals may be configured for either twostate or three-state operation.Use of the three-state address mode reduces the number of external components required for a DMA processor interface. The input clock frequency is user selectable for either 12 or 16 MHz. In the 12 MHz mode, the decoder operates at 24 MHz, providing superior word error rate and zero crossing distortion tolerance. The Busy, Service Request, and Subsystem Flag RT Status Word bits are provided as discrete pins, allowing for easy access by the subsystem. Various message timing and error flag indicators are provided to facilitate the subsystem interface. Data Device Corporation 105 Wilbur Place Bohemia, New York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com FOR MORE INFORMATION CONTACT: Technical Support: 1-800-DDC-5757 ext. 7771 (c) 2000 Data Device Corporation Data Device Corporation www.ddc-web.com 2 BU-65153 Rev H-07/07-0 ILLEGALIZATION AND STATUS INPUTS RESET R.T. ADDRESS CLOCK INPUT AND FREQUENCY SELECT BUS B TRANSMITTER INHIBIT BUS A BUSY SSFLAG SERVICE_REQUEST ILLCMD RESET RT_AD_LAT RT_AD_ERR RT_AD_P 3 2 1 3 2 1 BUS-25679 BUS-25679 RT_AD4-RT_AD0 CLK_SEL CLK 4 B DIR 7 8 5 55 ohms 55 ohms B XF B XF B DIR TX_INH 4 A DIR 7 8 5 55 ohms 55 ohms A XF A XF A DIR 1553 BUS I/O TRANSCEIVER B TRANSCEIVER A 5 * AND BIT WORD CURRENT COMMAND, *LAST COMMAND, STATUS, REGISTERS AND R.T. STATE MACHINE LOGIC ENCODER/ DECODER AND WATCHDOG TIMER FIGURE 1. BU-61703/5 BLOCK DIAGRAM STATUS, ILLEGALIZATION, AND TRANSMITTER INHIBIT LOGIC R.T. ADDRESS PARITY AND COMPARE LOGIC TX/RX B TX/RX B TX/RX A TX/RX A ADDRESS BUFFERS RT_FAIL ME GBR INCMD NBGRT LOWER DATA BUFFER DMA HANDSHAKE AND TRANSFER CONTROL LOGIC UPPER DATA BUFFER UPPER DATA BUS 14-BIT ADDRESS BUS LOWER DATA BUS ADDRESS TRI-STATE CONTROL DATA TRANSFER CONTROL DMA HANDSHAKE DATA BUS WIDTH SELECT MESSAGE TIMING SIGNALS A13-A0 D7-D0 ADDR_ENA WRT CS HS_FAIL DT_ACK DT_GRT DT_REQ DB_SEL D15-D8 TABLE 1. BUS-65153 SPECIFICATIONS PARAMETER ABSOLUTE MAXIMUN RATINGS Supply Voltage Logic + 5V Transceiver + 5 V - 15 V - 12 V Logic Voltage Input Range RECEIVER Differential Input Resistance (Bus-65153, Bus-65163, BUS- 65154, Bus-65164) (Notes 1 - 6) Differential Input Capacitance (Bus-65153, Bus-65163, BUS-65154, Bus-65164) (Notes 1 - 6) Threshold Voltage, Transformer Coupled, Measured on Stub Common Mode Voltage (Note 7) TRANSMITTER Differential Output Voltage Direct Coupled Accross 35 ohms, Measured on Bus Direct Coupled Accross 70 ohms Measured on Stub * BUS-65153, BUS-65163 (Note 10) * BUS-65154, BUS-65164 Output Noise, Differential (Direct Coupled) MIN TYP MAX TABLE 1. BUS-65153 SPECIFICATIONS UNITS - 0.3 - 0.5 + 0.3 + 0.3 7.0 7.0 - 18.0 - 18.0 V V V V - 0.5 Vcc+0.5 V 11 6 22 21 10 pF 0.860 VP-P 10 VPEAK 9 VP-P 27 27 10 POWER DISSIPATION BUS-65153, BUS-65163 Total Hybrid * Idle * 25% Duty Cycle * 50% Duty Cycle * 100% Duty Cycle Hottest Die * Idle * 25% Duty Cycle * 50% Duty Cycle * 100% Duty Cycle BUS-65154, BUS-65164 Total Hybrid * Idle * 25% Duty Cycle * 50% Duty Cycle * 100% Duty Cycle Hottest Die * Idle * 25% Duty Cycle * 50% Duty Cycle * 100% Duty Cycle VP-P VP-P mV P-P,diff Output Offset Voltage, Transformer Coupled Accross 70 Ohms Rise/Fall Time LOGIC VIH VIL IIH (VIN=VCC) IIL (VIN=GND) VOH (IOH = 0) VOH (IOH = max) VOL (IOL = 0) VOL (IOL = min) IOL IOH POWER SUPPLY REQUIREMENTS Voltages/Tolerances (BUS-65153, BUS-65163) + 5 V (Logic) + 5 V (CH A, CH B) - 15 V (CH A, CH B) Voltages/Tolerances (BUS-65154, BUS-65164) + 5 V (Logic) + 5 V (CH A, CH B) - 12 V (CH A, CH B) Current Drain (BUS-65153, BUS-65163, Note 9) + 5 V Logic (CH A, CH B) - 15 V (CH A, CH B) * Idle * 25% Duty Cycle * 50% Duty Cycle * 100% Duty Cycle Data Device Corporation www.ddc-web.com -250 100 150 250 mV 300 nsec 2.0 3.4 V V V V V V mA mA 4.5 4.5 -15.75 5.5 5.5 -14.25 V V V 4.5 4.5 -12.6 5.5 5.5 -11.4 V V V 65 115 mA 20 55 90 160 50 112 175 300 mA mA mA mA 0.8 20 20 -20 -20 Vcc+0.4 3.7 0.4 0.5 -3.4 5 MIN POWER SUPPLY REQUIREMENTS (CONTINUED) Current Drain (BUS-65154, BUS-65164, Note 9) + 5 V Logic (CH A, CH B) - 12 V (CH A, CH B) * Idle * 25% Duty Cycle * 50% Duty Cycle * 100% Duty Cycle k 0.500 20 18 PARAMETER CLOCK INPUT Frequency Nominal Value (Selectavle) * CLOCKSEL Input = Logic `0' * CLOCKSEL Input = Logic `1' Long Term Tolerance * 1553A Compliance * 1553B Compliance Short Term Tolerance, 1 Second * 1553A Compliance * 1553B Compliance Duty Cycle * 16 MHz * 12 MHz 1553 MESSAGE TIMING RT Response Time * 16 MHz * 12 MHz RT-to-RT No Response Timeout (Note 8) Transmitter Watchdog Timeout THERMAL Thermal Resistance, Junction-toCase, Hottest Die (JC) BUS-65153, BUS-65163 BUS-65154, BUS-65164 Operating Junction Temperature Storage Temperature Lead Temperature (Soldering for 10 seconds) 3 TYP MAX UNITS 65 115 mA 30 87 135 230 60 120 185 305 mA mA mA mA 0.625 0.850 1.075 1.525 1.325 1.963 2.600 3.875 W W W W 0.335 0.600 0.860 1.385 0.68 1.06 1.45 2.23 W W W W 0.685 0.985 1.285 1.885 1.295 1.727 2.160 3.035 W W W W 0.290 0.590 0.890 1.490 0.59 0.92 1.36 2.16 W W W W 16.0 12.0 6.00 6.18 18.25 -55 -65 MHz MHz 0.01 0.1 % % 0.001 0.01 % % 33 40 67 60 % % 6.5 6.5 18.9 6.96 6.76 19.5 S S S 668 S 5.54 5.54 C/W C/W C C C 160 150 +300 BU-65153 Rev H -07/07-0 Any subset of the possible 1553 commands (broadcast, T/R bit, subaddress, word count/mode code) may be optionally illegalized by means of an external PROM, PAL, or RAM device. An extensive amount of message validation is performed for each message received. Each word received is validated for correct sync type and sync encoding, Manchester II encoding, parity, and bit count. All messages are verified to contain a legal, defined Command Word and correct word count. If the BUS65153 is the receiving RT in an RT-to-RT transfer, it verifies that the T/R bit of the transmit Command Word is a one and that the transmitting RT responds in time and contains the correct RT address in its Status Word. TABLE 1. BUS-65153 SPECIFICATIONS PARAMETER PHYSICAL CHARACTERISTICS Size 70-pin, DIP, Flat Pack Weight 70-pin, DIP, Flat Pack MIN TYP 1.9 x 1.0 x 0.215 48.26 x 25.4 x 5.46 0.6 (17) MAX UNITS in (mm) oz (gm) Notes: Notes 1 through 6 are applicable to the Receiver Differential Resistance and Differential Capacitance specifications: (1) Specifications include both transmitter and receiver (tied together internally). (2) Measurement of impedance is directly between pins TX/RX A(B) and TX/RX A(B) of the BUS-65153 or BUS-65163 hybrid. (3) Assuming the connection of all power and ground inputs to the hybrid. (4) The specifications are applicable for both unpowered and powered conditions. (5) The specifications assume a 2 volt rms balanced, differential, sinusoidal input. The applicable frequency range is 75 KHz to 1 MHz. (6) Minimum resistance and maximum capacitance parameters are guaranteed,but not tested, over the operating range. (7) Assumes a common mode voltage within the frequency range of dc to 2 MHz, applied to pins of the isolation transformer on the stub side (either direct or transformer coupled), referenced to hybrid ground. Use a DDC recommended transformer or other transformer that provides an equivalent minimum CMRR. (8) RT-to-RT Timeout is measured from the Mid-Parity crossing of the Transmit Command word to the Mid-Sync crossing of the Transmitting RT Status word. (9) Current drain is for total hybrid (e.g., +5V supply current includes the sum of logic +5V supply current, channel A +5V supply current and channel B +5V supply current). Transmitting duty cycles assume one channel transmitting and alternate channel idle. (10) Compliant with 1760 applications. The 65153 may be operated from either a 12 MHz or 16 MHz clock input. In the 12 MHz mode, the decoder samples incoming data with both edges of the clock input. This, in effect, provides for 24 MHz decoder sampling. Benefits of the higher sampling rate include a wider tolerance for zero-crossing distortion and improved bit error rate performance. The BUS-65153 includes a hardwired R.T. address input. This includes 5 address lines, an address parity input, and an address parity error output. The RT address can also be latched internally by means of the address latching input signal RT_ADD_LAT. The 65153 supports command illegalization. Commands may be illegalized by asserting the output signal ILLCMD low approximately 5 ms after the mid-parity bit zerocrossing of the received Command Word. Command Words may be illegalized as a function of broadcast, T/R bit, subaddress, word count and/or mode code. An internal Built-in-Test (BIT) Word register is updated at the end of each message. The contents of the BIT Word Register are transmitted in response to a Transmit BIT Word Mode Command. The BUS-65153 provides a number of real-time output signals. These various signals provide indications of message start, message in progress, valid received message, message error, handshake fail, and looptest fail or transmitter timeout. INTRODUCTION GENERAL The BUS-65153 is a complete MIL-STD-1553 Remote Terminal (RT) bus interface unit. Contained in the hybrid are a dual trapezoidal transceiver and Manchester II encoder/decoder, and Remote Terminal (RT) protocol logic for MIL-STD-1553B. Also included are built-in self-test capability and a parallel subsystem interface. The subsystem interface includes a 14-bit address bus and a data bus that may be configured for either 8-bit or 16-bit DMA transfers. The BUS-65153 may be used in a wide variety of interface configurations. The 65153 has an 8/16-bit tri-state data bus and an address/control bus that may be pin programmed for either twostate or three-state operation. The three-state mode allows the BUS-65153 to be connected directly to the host processor's data, address, and control buses in a DMA configuration. The BUS-65153 includes standard DMA handshake signals (Request, Grant, and Acknowledge) as well as transfer control outputs (CS and WRT). The DMA interface may operate in either a 16-bit or 8-bit mode, supporting both word-wide and byte-wide transfers. The transceiver front end of the BUS-65153 is implemented by means of low-power bipolar analog monolithic and thick-film hybrid technology. The transceiver requires +5 V and -15 V only (no +15 V is required) and includes voltage source transmitters. The voltage source transmitters provide superior line driving capability for long cables and heavy amounts of bus loading. In addition, the monolithic transceivers provide a minimum stub voltage level of 20 volts peak-to-peak transformer coupled, making the BUS-65153 suitable for MIL-STD-1760 applications. The DMA interface also allows the 65153 to be interfaced directly to a simple system that doesn't have a microprocessor. This provides a low-cost 1553 interface for A/D and D/A converters, switch closures, and actuators. The BUS-65153 may also be used in a shared RAM interface configuration. By means of tri-state buffers and a very small amount of "glue" logic, the 65153 will store Command Words and access Data Words to/from dedicated "mailbox" areas in a shared RAM for each broadcast / T-R bit / subaddress / mode code. The receiver sections of the BUS-65153 are fully compliant with MIL-STD-1553B in terms of front end overvoltage protection, threshold and bit-error rate. The BUS-65153 implements all MIL-STD-1553 message formats, including all 13 of the 1553B dual redundant mode codes. Data Device Corporation www.ddc-web.com 4 BU-65153 Rev H-07/07-0 If a more elaborate shared RAM interface is needed, the BUS65153 may be interfaced to a BUS-66315 memory management unit. If a BUS-66315 is used, the address bus of the BUS-65153 is not used for accessing the system RAM (although the address outputs may still be used for command illegalizing). An 8/16-bit data bus, a 14-bit address bus, and six control signals are provided to facilitate communication with the parallel subsystem. The control signals include the standard DMA handshake signals DT_REQ, DT_GRT, DT_ACK as well as the transfer control outputs CS and WRT. HS_FAIL provides an indication to the subsystem of a handshake failure condition. The BUS-66315 provides an RT Lookup Table, allowing the mapping of the various T-R/subaddresses to user programmable areas in the BUS-66315's 64K x 16 shared RAM address space. The BUS-66315 also provides a stack area of RAM. The stack provides a chronology of all messages processed, storing a Block Status Word (message channel, completion, and validity information), an optional Time Tag Word and the received Command Word for each message processed. The BUS-66315 also provides maskable interrupts to the host processor for endof-message and/or message error conditions. Data is transferred between the subsystem and the BUS-65153 via a DMA handshake, initiated by the BUS-65153. A READ operation is defined to be the transfer of data from the subsystem to the BUS-65153. Conversely, a WRITE operation transfers data from the BUS-65153 to the subsystem. If the BUS-65153 is in 16-bit mode, data is transferred as a single 16-bit word. In 8-bit mode, data is transferred in a pair of byte transfers within the same DMA handshake cycle. The upper byte is transferred first with A0=1, followed by the lower byte with A0=0. ADDRESS MAPPING The memory allocation scheme for the BUS-65153 14-bit address bus is defined as follows: A13: A12: A11-A7: A6: A5-A1: A0: HANDSHAKE FAIL If the BUS-65153 (STIC) asserts DT_REQ and the subsystem does not respond with DT_GRT in time for the BUS-65153 to complete the word transfer, the HS_FAIL output will be asserted low to inform the subsystem of the handshake failure and bit D12 in the internal Built-In-Test (BIT) word is set to logic (c)1." If the handshake failure occurs on a data word read transfer (transmit command) the STIC will abort the current message processing and NOT transmit erroneous data back to the bus controller. In the case of a handshake failure on a write transfer (receive command word transfer, transmit command transfer, or a receive data word transfer) the STIC will set the handshake failure output and BIT word bit, and continue processing the current message. BROADCAST/OWNADDRESS TRANSMIT/RECEIVE SUBADDRESS 4-0 DATA/COMMAND WORD COUNT/CURRENT WORD COUNT UPPER/LOWER BYTE (8-bit mode only) The method of address mapping implemented by the BUS65153 provides for a "mailbox" allocation scheme for the storage of Command and Data Words. The address outputs A13 through A1 map directly into 8K words (16K bytes) of processor address space. A0 is used for upper/lower byte selection in the 8-bit DMA mode. The same address map is applicable for both the DMA and shared RAM (without the BUS-66315) interface configurations. The BUS-65153's addressing scheme maps messages in terms of broadcast/own address, transmit/receive, subaddress, and mode code. A 64-word message block is allocated for each T/R-subaddress. DMA READ OPERATION Whenever the BUS-65153 needs to read a word from the subsystem, it asserts the signal DT_REQ low. If the subsystem asserts DT_GRT in time, the BUS-65153 will then assert A13 through A1 (and A0 for the 8-bit mode), WRT high, along with DT_ACK and CS low to enable data from the subsystem. The received Command Word for all nonmode code messages is stored at relative word location zero (0) within the respective message block. For mode code messages, the address for the received Command Word is offset from location zero (0) within the message block for subaddress 0 or 31. The value of the address offset is equal to the mode code field of the respective Command Word (0 to 31). After the transfer of each Data Word has been completed, address bus outputs A5 through A1 are incremented. This provides the option of connecting the BUS-65153 address lines directly to the host processor's address bus to access the subsystem RAM, if desired. For nonmode code messages, the Data Words to be transmitted or received are accessed from (to) relative locations 32 through 63 within the message block. For mode code messages with a single Data Word that is not read from internal register, the address for the Data Word is offest from location 32 within the 64-word message block for subaddresses 0 and 31. The value of the address offset is equal to the mode code field of the received Command Word. DMA WRITE OPERATION Whenever the BUS-65153 needs to transfer data to the subsystem, it initiates a DMA WRITE cycle. The BUS-65153 asserts DT_REQ. The subsystem must respond with DT_GRT. If DT_GRT was received in time, the BUS-65153 will then assert DT_ACK. The BUS-65153 will then assert A13 through A1 (and A0 in 8-bit mode) and WRT low, followed by CS low. The subsystem may then use the rising edge of CS to latch the data. Similar to the DMA read operation, the address outputs A5 through A1 are incremented after the completion of a DMA WRITE operation. The Data Words transmitted in response to Transmit Last Command or Transmit BIT Word mode commands are accessed from a pair of internal registers. DMA INTERFACE Data Device Corporation www.ddc-web.com 5 BU-65153 Rev H -07/07-0 MESSAGE PROCESSING OPERATION The output of the illegalization PROM may be latched using a flip-flop and an AND gate (see FIGURE 2). The output signal INCMD from the STIC is used as the clock enable input to the flip-flop. The flip-flop is updated on every rising clock edge while INCMD is high, and is not updated while INCMD is low. This allows the output of the PROM to be updated on the last clock edge before INCMD is asserted low. Once INCMD is asserted, the clock enable input to the flip-flop is removed, thus preserving the value of the latched illegal bit. Following the receipt and transfer of a valid Command Word, the BUS-65153 will attempt to (1) transfer received 1553 data to thesubsystem, (2) read data from the subsystem for transmission on the 1553 bus, (3) transmit status (and possibly built-in-test) information to 1553, and/or (4) set status conditions. The BUS-65153 responds to all nonbroadcast messages with a 1553 Status Word. Illegalizing commands in the three-state mode of operation also requires the use of a latch. The latch must be updated during a word transfer since the address lines are normally in a high impedance state. FIGURE 3 illustrates a method of latching the output from the PROM using a flip-flop and the signal CS. RT ADDRESS RT Address (RT_AD 4-0, (RT_AD4 = MSB)) and RT Address Parity (RT_AD_P) should be programmed for a unique RT address and reflect an odd parity sum. The BUS-65153 will not respond to any MIL-STD-1553 commands or transfer received data from any nonbroadcast messages if an odd parity sum is not presented by RT_AD4-0 and RT_AD_P. An address parity error will be indicated by a low output on the RT_AD_ERR pin. The input signal RT_AD_LAT operates a transparent latch for RTAD4-RTAD0 and RTADP. If RT_AD_LAT is low the output of the latch tracks the value presented to the input pins. If RT_AD_LAT is high, the output of the internal latch becomes latched at the values presented when RT_AD_LAT was low. The signal CS is driven low during every word transfer. The only word transfer that takes place before the illegal command input (ILLCMD) input is sampled is the command word transfer. The word count field of the command word may be obtained directly from the lower 5 bits of the data bus. The subaddress, T/R, and broadcast signals are available on address lines A07-A13. Note that the signal CS will be asserted twice during a transfer in the 8-bit mode of operation. The word count field is located in the lower byte, which is presented during the second byte transfer. The second CS will, therefore, latch the appropriate value for ILLEGAL. COMMAND ILLEGALIZATION The BUS-65153 provides for command illegalization. If a command is illegalized, the BUS-65153 will set the Message Error bit and transmit its status word to the Bus Controller. No Data Words will be transmitted in response to an illegalized Transmit command. Data Words associated with an illegalized Receive command will, however, be presented to the subsystem. ILLCMD is sampled approximately 5 ms following the mid-parity bit zero crossing of the received Command Word (reference FIGURES 4-9). Command illegalization can be implemented using either a two-state or three-state address bus. An external PROM, PLD, or RAM device can be used to define the legality of specific commands. Any subset of the possible 1553 commands can be illegalized as a function of broadcast, T/R bit, subaddress, word count, and/or mode code. This method of latching the address lines places a constraint on the access time of the PROM and on the maximum request to grant time for the command word transfer. The access time of the PROM must be less than 195 ns. If the data bus grant signal is held off too long, the ILLCMD input will not be updated in time. The maximum request to grant time is equal to the following: tmax 16-bit @12 MHz 16-bit @16 MHz 8-bit @12 MHz 8-bit @16 MHz 2.455 2.720 1.940 2.205 ms ms ms ms TRANSMIT COMMAND (RT-TO-BC TRANSFER) Illegalizing commands in the two-state mode, based on broadcast, T/R bit, subaddress, and/or mode code, may be done by means of a programmable device such as a PROM. The address outputs from the STIC may be connected directly to the address inputs to a PROM. Illegalizing commands in the two-state mode, based on broadcast, T/R bit, subaddress, and word count requires an external latch to store the value of the word count field. The word count must be latched after the address lines A5...A1 are updated for the present command and before these address lines are cleared to 00000 for the command word transfer. If the BUS-65153 receives a valid Transmit Command Word that the subsystem determines is legal (input ILLCMD is high) and the subsystem is not BUSY (input BUSY is high), the BUS-65153 will initiate a transmit data response following transmission of the Status Word. This entails a handshake/read cycle for each Data Word, with the total number of Data Words to be transmitted specified by the Word Count field of the Command Word. A low on ILLCMD will result in the Message Error bit being set. No Data Words will be transmitted following transmission of the Status Word to an illegalized transmit command. A low on the BUSY input will set the BUSY bit in the Status Word; in this instance, only the Status Word will be transmitted, with no Data Words. The word count address lines (A5...A1) are multiplexed internally between the latched word count field of the command word, and the current word counter. While the signal INCMD is high (logic 1) these address lines reflect the word count field of the present command. While INCMD is low (logic 0) these signals represent the value of the current word counter, which is cleared to zero at the start of a message, and is incremented after each data word transfer. Data Device Corporation www.ddc-web.com transfer type RECEIVE COMMAND (BC-TO-RT TRANSFER) A DMA handshake will be initiated for each word received over the 1553 data bus. If successful, the respective handshake will be followed by a corresponding write cycle. A handshake timeout 6 BU-65153 Rev H-07/07-0 BUS-65153 A0 A1 A2 A3 A4 A01 A02 A03 A04 A05 WC WC WC WC WC 0 1 2 3 4 A07 A08 A09 A10 A11 SA SA SA SA SA A12 T/R A10 A13 BRO A11 A5 A6 A7 A8 A9 0 1 2 3 4 4Kx1 PROM D0 OE "STIC" ILLEGAL Q D Q 1 3 2 INCMD CLOCK CLOCK IN OSCILLATOR FIGURE 2. BUS-65153 TWO-STATE ILLEGALIZATION BUS-65153 "STIC" D00 D01 D02 D03 D04 WC WC WC WC WC A07 A08 A09 A10 A11 SA SA SA SA SA A12 T/R A10 A13 BRO A11 __ OE _______ ILLEGAL Q 0 1 2 3 4 0 1 2 3 4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 4Kx1 PROM D D Q __ CS FIGURE 3. BUS-65153 THREE-STATE ILLEGALIZATION Data Device Corporation www.ddc-web.com 7 BU-65153 Rev H -07/07-0 will not terminate transfer attempts for the remaining Data Words, error flagging or Status Word transmission. After the reception of a valid nonmode code receive Command Word followed by the correct number of valid Data Words and assuming that all words are successfully transferred to the subsystem, a negative pulse will be asserted on the output Good Block Received (GBR). BIT WORD The BUS-65153 provides an internally formulated Built-In-Test word. This word is transmitted to the BC in response to a Transmit Bit Word Mode Code Command. Internal Built-In-Test (BIT) Word Definition D15: D14: D13: D12: D11: D10: D09: D08: D07: D06: D05: D04: D03: RT-TO-RT TRANSFER ERRORS If the T/R bit of the "transmit" command in an RT-to-RT transfer is a zero, the transmitting RT does not respond in time or an address mismatch is detected in the transmitting RT's Status Word, the BUS-65153, as receiving RT, will classify the condition as a "Command error" and will not respond. RT STATUS, ERROR HANDLING, AND MESSAGE TIMING SIGNALS Message transfer errors are indicated by means of the HS_FAIL, ME, and RT_FAIL error indication outputs. Additional error detection and indication mechanisms include updating of the internal Status and BIT Word registers. D02: D01: The BUS-65153 provides a number of timing signals during the processing of 1553 messages. NBGRT provides a negative pulse output following the receipt of a 1553 Command Word. INCMD is asserted low when a new command is received. At the end of a message (either valid or invalid), INCMD transitions from low to high. Following the last data word of a valid nonmode code receive message, GBR is asserted low. ME is asserted as a low output following any detected error in a received message. D00: Transmitter Timeout Loop Test Failure - B Bus Loop Test Failure - A Bus Handshake Failure Bus B Transmitter Shutdown Bus A Transmitter Shutdown Terminal Flag Inhibited Ch A / Ch B High Word Count Low Word Count Incorrect Sync Type Received Invalid Word Received - Manchester or Parity Error RT-RT Transfer Response Error (no gap, data sync, address mismatch) RT-RT Transfer No Response Timeout RT-RT Transfer - T/R Error on Second Command or My Valid Address Command Word Contents Error Note: Bits 15 through 9 are cleared only following a RESET input or reception of a Reset Remote Terminal mode command. Bits 8 through 0 are updated as a result of every message processed. BIT WORD Bit Descriptions LOOPBACK TEST TRANSMITTER TIMEOUT: Set if the STIC's failsafe timer detected a fault condition. The transmitter timeout circuit will automatically shut down the CH. A or CH. B transmitter if it transmits for longer than 668 S. The BUS-65153 performs a loopback self-test at the end of each nonbroadcast message processed. The loopback test consists of the following verifications: (1) The received version of every transmitted word is verified for validity (encoding, bit count, parity) and correct sync type; (2) The first transmitted word (RT Status Word) is checked for correct RT Address field; and (3) The received version of the last transmitted word is verified by means of a bit-by-bit comparison to the transmitted version of the word. If there is a transmitter timeout (668 ms) and/or the loopback test fails for one or more transmitted words, the Terminal Flag Status Word bit will be set in response to the next nonbroadcast message. CH. B LOOP TEST FAILURE, CH. A LOOP TEST FAILURE: A loopback test is performed on the transmitted portion of every non-broadcast message. A validity check is performed on the received version of every word transmitted by the STIC. In addition, a bit-by-bit comparison is performed on the last word transmitted by the RT for each message. If either the received version of any transmitted word does not match the transmitted version and/or the received version of the last transmitted word is determined to be invalid (sync, encoding, bit count, parity), or a failsafe timeout occurs on the respective channel, the LOOP TEST FAILURE bit for the respective bus channel will be set. STATUS WORD The Broadcast Command Received bit is formulated internally. The Message Error Status bit will be set if the current command is a Transmit Status Word or Transmit Last Command mode command and if there was an error in the data portion of the previous receive message. Message Error will also be set if ILLCMD has been sampled low for the current message. ILLCMD, Service Request, Busy, and Subsystem Flag will be sampled from their respective Status input pins approximately 5 ms following the mid-parity bit zero crossing of the received Command Word. Data Device Corporation www.ddc-web.com HANDSHAKE FAILURE: If this bit is set, it indicates that the subsystem had failed to respond with the DMA handshake input DTGRT asserted within the allotted time in response to the STIC asserting DTREQ. The allotted time for the subsystem's DTREQto-DTGRT response time is approximately 3.0 to 3.7 ms for a DMA write cycle and approximately 15.1 to 15.3 ms for a DMA read cycle. CH. B TRANSMITTER SHUTDOWN, CH. A TRANSMITTER SHUTDOWN: Indicates that the transmitter on the respective bus channel has been shut down by a Transmitter shutdown mode code command received on the alternate channel. If an Override 8 BU-65153 Rev H-07/07-0 transmitter shutdown mode code command is received on the alternate channel, this bit will revert back to logic "0". MODE CODES All 13 of the dual redundant MIL-STD-1553B mode codes are implemented by the BUS-65153. Two mode codes, Transmit Vector Word and Synchronize (with data) involve data transfer with the subsystem. For the Transmit BIT Word mode code, the internally formulated BIT Word is transmitted. TABLE 2 provides a summary of the 1553B mode codes supported by the BUS65153. TERMINAL FLAG INHIBITED: Set to logic "1" if the STIC's Terminal Flag RT Status bit has been disabled by an Inhibit Terminal Flag mode code command. Will revert to logic "0" if an Override inhibit terminal flag mode code command is received. CH. A/CH. B: Logic "0" if the previous message was received on CH.A, logic "1" if the previous message was received on CH. B. HIGH WORD COUNT: Set to logic "1" if the previous message had a high word count error. TABLE 2. MIL-STD-1553B MODE CODES T/R BIT LOW WORD COUNT: Set to logic "1" if the previous message had a low word count error. INCORRECT SYNC TYPE RECEIVED: If set, indicates that the STIC detected a Command sync in a received Data Word. INVALID WORD: Indicates that the STIC received one or more words containing one or more of the following error types: sync field error, Manchester encoding error, parity error, and/or bit count error. RT-to-RT GAP/SYNC/ADDRESS ERROR: This bit is set if the STIC RT is the receiving RT for an RT-to-RT transfer and one or more of the following occur: (1) If the transmitting RT responds with a response time of less than 4 ms, per MIL-STD-1553B (mid-parity bit to mid-sync); i.e., less than 2 ms dead time; and/or (2) There is an incorrect sync type or format error (encoding, bit count, and/or parity error) in the transmitting RT Status Word; and/or (3) The RT address field of the transmitting RT Status Word does not match the RT address in the transmit Command Word. RT-to-RT RESPONSE TIMEOUT: If set, indicates that, for the previous message, the STIC was the receiving RT for an RT-toRT transfer and that the transmitting RT either did not respond or responded later than the STIC's RT-to-RT Timeout time. The STIC's RT-to-RT Response Timeout Time is defined as the time from the mid-bit crossing of the parity bit of the transmit Command Word to the mid-sync crossing of the transmitting RT Status Word. The value of the STIC's RT-to-RT Response Timeout time is 18.9 S. RT-to-RT SECOND COMMAND ERROR: If the STIC is the receiving RT for an RT-to-RT transfer, this bit set indicates one or more of the following error conditions in the transmit Command Word: (1) T/R bit = logic "0"; (2) subaddress = 00000 or 11111; (3) Same RT Address field as the receive Command Word. COMMAND WORD CONTENTS ERROR: Indicates a received command word is not defined in accordance with MIL-STD1553B. This includes the following undefined Command Words: (1) The Command Word is a non-mode code, broadcast, transmit command; (2) A message with a T/R bit of "0", a subaddress/mode field of 00000 or 11111 and a mode code field between 00000 and 01111; (3) A mode code command that is not permitted to be broadcast (e.g., Transmit Status) is sent to the broadcast address 11111. Data Device Corporation www.ddc-web.com MODE CODE FUNCTION DATA WORD BROADCAST ALLOWED 1 00000 Dynamic Bus Control No No 1 00001 Synchronize No Yes 1 00010 Transmit Status Word No No 1 00011 Initiate Self Test No Yes 1 00100 Transmitter Shutdown No Yes 1 00101 Override Transmitter Shutdown No Yes 1 00110 Inhibit Terminal Flag No Yes 1 00111 Override Inhibit Terminal Flag No Yes 1 01000 Reset Remote Terminal No Yes 1 0100111111 RESERVED No TBD 1 10000 Transmit Vector Word From Subsystem No 0 10001 Synchronize with Data To Subsystem Yes 1 10010 Transmit Last Command From Internal Register No 0 10100 Selected Transmitter Shutdown (See Note) To Subsystem Yes 0 10101 Override Selected Transmitter Shutdown (See Note) To Subsystem Yes 1 10011 Terrminal BIT Word From Internal Register No 0 1011011111 RESERVED Yes TBD 1 1011011111 RESERVED Yes TBD Note: Terminal responds with Clear Status but no action is taken, assuming a valid Command Word and any valid Data Word is received. 9 BU-65153 Rev H -07/07-0 TABLE 3B. MODE CODE MEMORY MAP FOR SUBADDRESS 00000,T/R = 0 TABLE 3. OVERALL MEMORY MAP Note: TABLES 3 and 3A-3D are byte-oriented addressing. ADDRESS (HEX) ADDRESS FUNCTION (HEX) 0000, 0001 COMMAND WORD, T/R = 0, MODE CODE 00000 (INVALID) * * * * * * FUNCTION MODE CODE (SUBADDRESS 0000, T/R = 0), See (TABLE 3B) 0080-00FF RECEIVE, SUBADDRESS 1 (See TABLE 3A) 0000-007F 0100-017F RECEIVE, SUBADDRESS 2 (See TABLE 3A) * * * * * * 001E, 001F COMMAND WORD, T/R = 0, MODE CODE 01111 (INVALID) 020E, 0021 0022, 0023 0F00-0F7F RECEIVE, SUBADDRESS 30 (See TABLE 3A) MODE CODE (SUBADDRESS 11111), 0F80-0FFF T/R = 1 (SeeTABLE 3C) MODE CODE (SUBADDRESS 00000), 1000-107F T/R = 1 (SeeTABLE 3D) 1080-10FF TRANSMIT, SUBADDRESS 1 (See TABLE 3A) 1100-117F TRANSMIT, SUBADDRESS 2 (See TABLE 3A) * * * * * * 1F00-1F7F TRANSMIT SUBADDRESS 30 (See TABLE 3A) MODE CODE (SUBADDRESS 11111), 1F80-1FFF T/R = 1 (SeeTABLE 3E) BROADCAST MODE CODE (SUBADDRESS 00000), 2000-207F T/R = 0 (Note: Use TABLE 3B, but increase address by 2000) * * * 003E, 003F 0040, 005F 0060, 0063 0062, 0063 * COMMAND WORD, T/R = 0, MODE CODE 10000 (RESERVED) COMMAND WORD, T/R = 0, MODE CODE 10001 (SYNC WITH DATA) * * * COMMAND WORD, T/R = 0, MODE CODE 11111 (RESERVED) NOT USED (MODE CODES WITHOUT DATA) DATA WORD FOR MODE CODE 10000, T/R = 0 (RESERVED) DATA WORD FOR MODE CODE 10001, T/R = 0 (SYNC WITH DATA) * * * * * 007E, 007F DATA WORD FOR MODE CODE 11111, T/R = 0 (RESERVED) 2080-20FF BROADCAST, RECEIVE, SUBADDRESS 1 (See TABLE 3A) TABLE 3C. MODE CODE MEMORY MAP FOR SUBADDRESS 11111 T/R = 0 2100-217F BROADCAST, RECEIVE, SUBADDRESS 2 (See TABLE 3A) * * * * * * ADDRESS FUNCTION (HEX) 0F80, 0F81 COMMAND WORD, T/R = 0, MODE CODE 00000 (UNDEFINED) * * 2F00-2F7F BROADCAST, RECEIVE, SUBADDRESS 30 (See TABLE 3A) BROADCAST MODE CODE (SUBADDRESS 11111), 2F80-2FFF T/R = 0 (Note: Use TABLE 3C, but increase address by 2000) BROADCAST MODE CODE (SUBADDRESS 00000), 3000-307F T/R = 0 (Note: Use TABLE 3D, but increase address by 2000) 3080-30FF BROADCAST, TRANSMIT, SUBADDRESS 1 (UNDEFINED) 3100-317F BROADCAST, TRANSMIT, SUBADDRESS 2 (UNDEFINED) * * * * * * 3F00-3F7F BROADCAST, TRANSMIT, SUBADDRESS 30 (UNDEFINED) BROADCAST MODE CODE (SUBADDRESS 11111), 3F80-3FFF T/R = 1 (Note: Use TABLE 3E, but increase address by 2000) * * 009E, 009F COMMAND WORD, T/R = 0, MODE CODE 01111 (UNDEFINED) 0FA0, 0FA1 COMMAND WORD, T/R = 0, MODE CODE 10000 (RESERVED) 0FA2, 0FA3 COMMAND WORD, T/R = 0, MODE CODE 10001 (SYNC WITH DATA) * * * * * TABLE 3A. TYPICAL MEMORY MAP OF EACH NONMODE CODE SUBADDRESS, 64 WORD BLOCK OFFSET (HEX) COMMAND WORD 0002, 003F NOT USED 0040, 0041 DATA WORD 0 0042, 0043 DATA WORD 1 * * * 007E, 007F DATA WORD 31 Data Device Corporation www.ddc-web.com * 0FBE, 0FBF COMMAND WORD, T/R = 0, MODE CODE 11111 (RESERVED) 0FC0, 0FDF NOT USED (MODE CODES WITHOUT DATA) FUNCTION 0000, 0001 * * 0FE0, 0FE1 DATA WORD FOR MODE CODE 10000, T/R = 0 (RESERVED) 0FE2, 0FE3 DATA WORD FOR MODE CODE 10001, T/R = 0 (SYNC WITH DATA) * * * * * * * * * 0FFE, 0FFF DATA WORD FOR MODE CODE 11111, T/R = 0 (RESERVED) 10 BU-65153 Rev H-07/07-0 TABLE 3D. MODE CODE MEMORY MAP FOR SUBADDRESS 00000, T/R = 1 ADDRESS (HEX) 1000, 1001 TABLE 3E. MODE CODE MEMORY MAP FOR SUBADDRESS 11111, T/R = 1 ADDRESS (HEX) FUNCTION COMMAND WORD, T/R = 1, MODE CODE 00000 (DYNAMIC BUS CONTROL) 1F80, 0F81 * * * * * * * * * COMMAND WORD, T/R = 1, MODE CODE 10001 RESERVED) * * * * * * 1FA2, 1FA3 COMMAND WORD, T/R = 1, MODE CODE 10001(RESERVED) * * * ** * 103E, 103F COMMAND WORD,T/R = 1, MODECODE 11111 (RESERVED) 1040, 105F NOT USED (MODE CODES WITHOUT DATA) 1FBE, 1FBF 1060, 1061 DATA WORD FOR MODE CODE 10000, T/R = 1 (TRANSMIT VECTOR WORD) 1FC0, 1FDF 1062, 1063 DATA WORD FOR MODE CODE 10001, T/R = 1 (RESERVED) 1FE0, 1FE1 * * * * 1FE2, 1FE3 * * * * * 107E, 107F DATA WORD FOR MODE CODE 11111, T/R = 1 (RESERVED) Data Device Corporation www.ddc-web.com COMMAND WORD,T/R = 1, MODE CODE 00000 (DYNAMICBUSCONTROL) * * * COMMAND WORD, T/R = 1, MODE CODE 01111 1F9E, 1F9F (RESERVED) COMMAND WORD, T/R = 1, MODE CODE 10000 1FA0, 1FA1 (TRANSMIT VECTOR WORD) 101E, 101F COMMAND WORD,T/R = 1, MODECODE 01111 (RESERVED) COMMAND WORD, T/R = 1, MODE CODE 10000 1020, 1021 (TRANSMIT VECTOR WORD) 1022, 1023 FUNCTION 11 ** COMMAND WORD, T/R = 1, MODE CODE 11111 (RESERVED) NOT USED (MODE CODES WITHOUT DATA) DATA WORD FOR MODE CODE 10000, T/R = 1 (TRANSMIT VECTOR WORD) DATA WORD FOR MODE CODE 10001, T/R = 1 (RESERVED) * * * DATA WORD FOR MODE CODE 11111, T/R = 1 (RESERVED) BU-65153 Rev H -07/07-0 MID-PARITY t12 1553 BUS TRANSMIT COMMAND t1 t2 ______ NBGRT ___ _______ ME, HS_FAIL t11 t3 _______ A6 (COMMAND/DATA) t4 _________ ___ LMC, A13(BRDCST/OWN ADDRS), _ A12(T/R),A11-A7(SA4-SA0) PREVIOUS COMMAND A5-A1 (WC/MC4-0, CWC4-0) PREVIOUS COMMAND PRESENT WC C t8 t5 _____ INCMD ____ WRT (NOTE 1) _____ _____ _____ DTREQ, DTGRT, __ DTACK, DATA15-0, CS (NOTE 1) t6 t9 t7 _______ _______ ILLEGAL, SERVREQ, ______ ____ SSFLAG, BUSY t10 ___ GBR ______ RTFAIL FIGURE 4. RT TO BC (TRANSMIT) TIMING SYMBOL MAX UNITS t1(@12MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT DESCRIPTION 0.97 MIN TYP 1.56 ms t1(@16MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT 0.87 1.38 ms t2(@12MHz) NBGRT PULSE WIDTH 140 190 ns t2(@16MHz) NBGRT PULSE WIDTH 100 150 ns t3 NBGRT RISING EDGE TO A6 FALLING EDGE 45 ns t4(@12MHz) NBGRT FALLING EDGE TO ADDRESS VALID 300 410 ns t4(@16MHz) NBGRT FALLING EDGE TO VALID ADDRESS 220 330 ns t5(@12MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 800 865 ns t5(@16MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 590 655 ns t6(@12MHz) NBGRT FALLING EDGE TO START OF COMMAND WORD TRANSFER CYCLE (Note 2) 1.19 1.28 ms t6(@16MHz) NBGRT FALLING EDGE TO START OF COMMAND WORD TRANSFER CYCLE (Note 2) 0.88 0.97 ms t7 NBGRT FALLING EDGE TO VALID STATUS INPUTS 4.1 ms t8 INCMD FALLING EDGE TO CWC VALID t9 DATA TRANSFER CYCLE TIME (Notes 2,3,4) t10 STATUS INPUTS HOLD TIME t11(@12MHz) 5 60 ns See Note 4 ms NBGRT RISING TO A6 RISING (Note 5) 3 ms t11(@16MHz) NBGRT RISING TO A6 RISING (Note 5) 3 ms t12(@12MHz) RT RESPONSE TIME 6.18 6.96 ms t12(@16MHz) RT RESPONSE TIME 6.0 6.76 ms Data Device Corporation www.ddc-web.com 500 12 ns BU-65153 Rev H-07/07-0 MID-SYNC MID-SYNC MID-SYNC DATA STATUS MID-PARITY DATA COMMAND CWC=1 CWC=0 CWC=2 t16 t16 t14 t18 t17 t15 t9 t15 t9 t13 FIGURE 4. RT TO BC (TRANSMIT) TIMING (CONTINUED) SYMBOL DESCRIPTION t13 MID-SYNC CROSSING OF STATUS RESPONSE TO RTFAIL RISING t14(@12MHz) MID-SYNC CROSSING OF STATUS RESPONSE TO WRT RISING t14(@16MHz) t15(@12MHz) MIN TYP MAX UNITS 100 ns 0.920 1.405 ms MID-SYNC CROSSING OF STATUS RESPONSE TO WRT RISING 0.840 1.305 s MID-SYNC CROSSING OF TRANSMITTED DATA TO START OF DATA TRANSFER CYCLE (Note 2) 1.700 2.085 s t15(@16MHz) MID-SYNC CROSSING OF TRANSMITTED DATA TO START OF DATA TRANSFER CYCLE (Note 2) 1.430 1.795 s t16 END OF DATA TRANSFER CYLE TO VALID NEXT WC (Note 3) t17(@12MHz) MID-SYNC CROSSING OF LAST DATA WORD TO WRT FALLING t17(@16MHz) 18(@12MHz) t18(@16MHz) 60 ns 0.965 1.365 s MID-SYNC CROSSING OF LAST DATA WORD TO WRT FALLING 0.880 1.260 s MID-PARTIY CROSSING OF LAST DATA WORD TO INCMD RISING 1.010 1.470 s MID-PARTIY CROSSING OF LAST DATA WORD TO INCMD RISING 0.910 1.350 s Notes: 1)IF ADDR_ENA IS LOGIC "1", CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED (DT_ACK = LOGIC "0"). 2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCES t6 AND t15 ARE DEFINED AS THE FALLING EDGE OF DT_REQ. 3)THE TRAILING EDGE OF REFERENCE t9 AND THE LEADING EDGE OF TIME REFERENCE t16 ARE DEFINED AS THE RISING EDGE OF DT_REQ. 4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES. 5)IF THE COMMAND WORD TRANSFER CYCLE IS NOT COMPLETE (i.e., DT_REQ IS STILL LOGIC LOW) BY THE TIME INDICATED BY THE TRAILING EDGE OF t11, A6 WILL BE HELD LOW UNTIL THE AFTER TRANSFER CYCLE IS COMPLETE (60 ns MAX AFTER THE RISING EDGE OF DT_REQ). Data Device Corporation www.ddc-web.com 13 BU-65153 Rev H -07/07-0 MID-PARITY RECEIVE COMMAND 1553 BUS DATA t1 _____ NBGRT t2 __ _______ ME, HS_FAIL _______ A6 (COMMAND/DATA) t3 t4 ___ _________ LMC, A13(BRDCST/OWN ADDRS), _ A12(T/R),A11-A7(SA4-SA0) PREVIOUS COMMAND A5-A1 (WC/MC4-0, CWC4-0) PREVIOUS COMMAND PRESENT COMMAND WC t8 t5 _____ INCMD ___ WRT (NOTE 1) _____ _____ _____ DTREQ, DTGRT, DTACK, __ DATA15-0, CS (NOTE 1) t6 t9 t7 _______ _______ ILLEGAL, SERVREQ, ______ ____ SSFLAG, BUSY t10 ___ GBR ______ RTFAIL FIGURE 5. BC TO RT (RECEIVE) TIMING MAX UNITS t1(@12MHz) SYMBOL COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT DESCRIPTION 0.97 MIN 1.56 s t1(@16MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT 0.87 1.38 s t2(@12MHz) NBGRT PULSE WIDTH 140 190 ns t2(@16MHz) NBGRT PULSE WIDTH 100 150 ns t3 NBGRT RISING EDGE TO A6 FALLING EDGE 45 ns t4(@12MHz) NBGRT FALLING EDGE TO ADDRESS VALID, LMC 300 410 ns t4(@16MHz) NBGRT FALLING EDGE TO VALID ADDRESS, LMC 220 330 ns t5(@12MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 800 865 ns t5(@16MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 590 655 ns t6(@12MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE 1.19 1.28 s t6(@16MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE (Note 2) 0.88 0.97 s t7 NBGRT FALLING EDGE TO VALID STATUS INPUTS 4.1 s t8 INCMD FALLING EDGE TO CWC VALID 60 ns 5 TYP See Note 4 s t9 DATA TRANSFER CYCLE TIME (Notes 2,3,4) t10 STATUS INPUTS HOLD TIME 500 t11(@12MHz) FIRST DATA WORD MID-PARITY CROSSING TO A6 RISING EDGE 820 1205 ns t11(@16MHz) FIRST DATA WORD MID-PARITY CROSSING TO A6 RISING EDGE 720 1025 ns Data Device Corporation www.ddc-web.com 14 ns BU-65153 Rev H-07/07-0 MID-PARITY MID-SYNC t14 MID-PARITY MID-PARITY DATA STATUS t11 ND PRESENT COMMAND CWC=0 CWC=1 CWC=2 t12 t13 t9 t12 t13 t16 t9 t17 t18 t15 FIGURE 5. BC TO RT (RECEIVE) TIMING SYMBOL DESCRIPTION t12 END OF DATA TRANSFER CYLE TO VALID NEXT WC (Note 3) t13(@12MHz) MID-PARITY CROSSING OF RECEIVED DATA WORD TO START OF DATA TRANSFER CYCLE (Note 2) t14(@12MHz) t14(@16MHz) t15 MID-SYNC CROSSING OF STATUS RESPONSE TO RTFAIL RISING t16(@12MHz MID-PARITY CROSSING OF STATUS RESPONSE TO INCMD RISING t16(@16MHz) MIN TYP MAX UNITS 60 ns 1.52 1.94 ms RT RESPONSE TIME 6.18 6.96 s RT RESPONSE TIME 6.0 6.76 s 100 s 3.36 3.57 s MID-PARITY CROSSING OF STATUS RESPONSE TO INCMD RISING 3.26 3.46 s t16(@12MHz) MID-PARITY CROSSING OF STATUS RESPONSE TO GBR FALLING 3.23 3.37 s t17(@16MHz) MID-PARITY CROSSING OF STATUS RESPONSE TO GBR FALLING 3.17 3.29 s t18(@12MHz) GBR PULSE WIDTH 140 190 t18(@16MHz GBR PULSE WIDTH 100 150 ns Notes: 1)IF ADDR_ENA IS LOGIC "1", CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED (DT_ACK = LOGIC "0"). 2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCES t6 AND t13 ARE DEFINED AS THE FALLING EDGE OF DT_REQ. 3)THE TRAILING EDGE OF REFERENCE t9 AND THE LEADING EDGE OF TIME REFERENCE t12 ARE DEFINED AS THE RISING EDGE OF DT_REQ. 4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES. Data Device Corporation www.ddc-web.com 15 BU-65153 Rev H -07/07-0 MID-PARITY 1553 BUS RECEIVE COMMAND TRANSMIT COMMAND t1 _____ NBGRT __ _______ ME, HS_FAIL _______ A6 (COMMAND/DATA) t4 ___ _________ LMC, A13(BRDCST/OWN ADDRS), _ A12(T/R),A11-A7(SA4-SA0) PREVIOUS COMMAND A5-A1 (WC/MC4-0, CWC4-0) PREVIOUS COMMAND t5 _____ INCMD ___ WRT (NOTE 1) _____ _____ _____ DTREQ, DTGRT, ___ DTACK, DATA15-0, CS (NOTE 1) t _______ _______ ILLEGAL, SERVREQ, ______ ____ SSFLAG, BUSY ___ GBR ______ RTFAIL FIGURE 6. RT TO RT (TRANSMIT) TIMING SYMBOL DESCRIPTION MIN TYP MAX UNITS t1(@12MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT 0.97 1.56 s t1(@16MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT 0.87 1.38 s t2(@12MHz) NBGRT PULSE WIDTH 140 190 ns t2(@16MHz) NBGRT PULSE WIDTH 100 150 ns t3 NBGRT RISING EDGE TO A6 FALLING EDGE 45 ns t4(@12MHz) NBGRT FALLING EDGE TO ADDRESS VALID 300 410 ns t4(@16MHz) NBGRT FALLING EDGE TO VALID ADDRESS 220 330 ns t5(@12MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 800 865 ns t5(@16MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 590 655 ns t6(@12MHz) NBGRT FALLING EDGE TO START OF COMMAND WORD TRANSFER CYCLE (Note 2) 1.19 1.28 s t6(@16MHz) NBGRT FALLING EDGE TO START OF COMMAND WORD TRANSFER CYCLE (Note 2) 0.88 0.97 s t7 NBGRT FALLING EDGE TO VALID STATUS INPUTS 4.1 s t8 INCMD FALLING EDGE TO CWC VALID 60 ns 5 See Note 4 s t9 DATA TRANSFER CYCLE TIME (Notes 2,3,4) t10 STATUS INPUTS HOLD TIME t11(@12MHz) NBGRT RISING TO A6 RISING (Note 5) 3 s t11(@16MHz) NBGRT RISING TO A6 RISING (Note 5) 3 s t12(@12MHz) RT RESPONSE TIME 6.18 6.96 s t12(@16MHz) RT RESPONSE TIME 6.0 6.76 s Data Device Corporation www.ddc-web.com 500 16 ns BU-65153 Rev H-07/07-0 MID-SYNC t12 MID-SYNC MID-SYNC STATUS DATA MID-PARITY DATA t2 t11 t3 PRESENT COMMAND WC CWC=0 CWC=2 CWC=1 t8 t5 t16 t16 t14 t6 t9 t7 t17 t15 t9 t15 t9 t10 t13 FIGURE 6. RT TO RT (TRANSMIT) TIMING (CONTINUED) SYMBOL DESCRIPTION MIN TYP MAX UNITS 100 ns t13 MID-SYNC CROSSING OF STATUS RESPONSE TO RTFAIL RISING t14(@12MHz) MID-SYNC CROSSING OF STATUS RESPONSE TO WRT RISING 0.920 1.405 s t14(@16MHz) MID-SYNC CROSSING OF STATUS RESPONSE TO WRT RISING 0.840 1.305 s t15(@12MHz) MID-SYNC CROSSING OF TRANSMITTED DATA TO START OF DATA TRANSFER CYCLE (Note 2) 1.700 2.085 s t15(@16MHz) MID-SYNC CROSSING OF TRANSMITTED DATA TO START OF DATA TRANSFER CYCLE (Note 2) 1.430 1.795 s t16 END OF DATA TRANSFER CYLE TO VALID NEXT WC (Note 3) 60 ns t17(@12MHz MID-SYNC CROSSING OF LAST DATA WORD TO WRT FALLING 0.965 1.365 s t17(@16MHz) MID-SYNC CROSSING OF LAST DATA WORD TO WRT FALLING 0.880 1.260 s t18(@12MHz) MID-PARTIY CROSSING OF LAST DATA WORD TO INCMD RISING 1.010 1.470 s 18(@16MHz) MID-PARTIY CROSSING OF LAST DATA WORD TO INCMD RISING 0.910 1.350 s Notes: 1)IF ADDR_ENA IS LOGIC "1", CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED (DT_ACK = LOGIC "0"). 2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCES t6 AND t15 ARE DEFINED AS THE FALLING EDGE OF DT_REQ. 3)THE TRAILING EDGE OF REFERENCE t9 AND THE LEADING EDGE OF TIME REFERENCE t16 ARE DEFINED AS THE RISING EDGE OF DT_REQ. 4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES. 5)IF THE COMMAND WORD TRANSFER CYCLE IS NOT COMPLETE (i.e., DT_REQ IS STILL LOGIC LOW) BY THE TIME INDICATED BY THE TRAILING EDGE OF t11, A6 WILL BE HELD LOW UNTIL THE AFTER TRANSFER CYCLE IS COMPLETE (60 ns MAX AFTER THE RISING EDGE OF DT_REQ). Data Device Corporation www.ddc-web.com 17 BU-65153 Rev H -07/07-0 MID-PARITY TRANSMIT COMMAND RECEIVE COMMAND 1553 BUS t1 t2 _____ NBGRT __ _______ ME, HS_FAIL t3 t11 _______ A6 (COMMAND/DATA) t4 ___ _________ LMC, A13(BRDCST/OWN ADDRS), _ A12(T/R),A11-A7(SA4-SA0) PREVIOUS COMMAND A5-A1 (WC/MC4-0, CWC4-0) PREVIOUS COMMAND PRESENT COMMAND WC t5 _____ INCMD CWC=0 t8 ___ WRT (NOTE 1) _____ _____ _____ DTREQ, DTGRT, __ DTACK, DATA15-0, CS (NOTE 1) t6 t9 t7 _______ _______ ILLEGAL, SERVREQ, ______ ____ SSFLAG, BUSY t10 ___ GBR ______ RTFAIL FIGURE 7. RT TO RT (RECEIVE) TIMING SYMBOL DESCRIPTION MIN TYP MAX UNITS t1(@12MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT 0.97 1.56 s t1(@16MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT 0.87 1.38 s t2(@12MHz) NBGRT PULSE WIDTH 140 190 ns t2(@16MHz) NBGRT PULSE WIDTH 100 150 ns t3 NBGRT RISING EDGE TO A6 FALLING EDGE 45 ns t4(@12MHz) NBGRT FALLING EDGE TO ADDRESS VALID, LMC 300 410 ns t4(@16MHz) NBGRT FALLING EDGE TO VALID ADDRESS, LMC 220 330 ns t5(@12MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 800 865 ns t5(@16MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 590 655 ns t6(@12MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE 1.19 1.28 s t6(@16MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE (Note 2) 0.88 0.97 s t7 NBGRT FALLING EDGE TO VALID STATUS INPUTS 4.1 s t8 INCMD FALLING EDGE TO CWC VALID 60 ns t9 DATA TRANSFER CYCLE TIME (Notes 2,3,4) t10 STATUS INPUTS HOLD TIME 500 t11(@12MHz) A6 PULSE WIDTH 820 1205 ns t11(@16MHz) A6 PULSE WIDTH 720 1025 ns Data Device Corporation www.ddc-web.com 5 See Note 4 18 s ns BU-65153 Rev H-07/07-0 MID-PARITY MID-SYNC t14 MID-PARITY STATUS MID-PARITY DATA DATA STATUS CWC=1 CWC=2 t12 t13 t9 t12 t13 t16 t9 t17 t18 t15 FIGURE 7. RT TO RT (RECEIVE) TIMING (CONTINUED) DESCRIPTION SYMBOL t12 END OF DATA TRANSFER CYLE TO VALID NEXT WC (Note 3) t13(@12MHz) MID-PARITY CROSSING OF RECEIVED DATA WORD TO START OF DATA TRANSFER CYCLE (Note 2) t13(@16MHz) t14(@12MHz) MIN TYP MAX UNITS 60 ns 1.52 1.94 s MID-PARITY CROSSING OF RECEIVED DATA WORD TO START OF DATA TRANSFER CYCLE (Note 2) 1.23 1.57 s RT RESPONSE TIME 6.18 6.96 s t14(@16MHz) RT RESPONSE TIME 6.0 6.76 s t15 MID-SYNC CROSSING OF STATUS RESPONSE TO RTFAIL RISING 100 ns t16(@12MHz) MID-PARITY CROSSING OF STATUS RESPONSE TO INCMD RISING 3.36 3.57 s t16(@16MHz) MID-PARITY CROSSING OF STATUS RESPONSE TO INCMD RISING 3.26 3.45 s t17(@12MHz) MID-PARITY CROSSING OF STATUS RESPONSE TO GBR FALLING 3.23 3.37 s t17(@16MHz) MID-PARITY CROSSING OF STATUS RESPONSE TO GBR FALLING 3.17 3.29 s 18(@12MHz) GBR PULSE WIDTH 140 190 ns t18(@16MHz) GBR PULSE WIDTH 100 150 ns Notes: 1)IF ADDR_ENA IS LOGIC "1", CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED (DT_ACK = LOGIC "0"). 2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCES t6 AND t13 ARE DEFINED AS THE FALLING EDGE OF DT_REQ. 3)THE TRAILING EDGE OF REFERENCE t9 AND THE LEADING EDGE OF TIME REFERENCE t12 ARE DEFINED AS THE RISING EDGE OF DT_REQ. 4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES. Data Device Corporation www.ddc-web.com 19 BU-65153 Rev H -07/07-0 MID-PARITY 1553 BUS RECEIVE COMMAND t1 _____ NBGRT __ ME _______ HS_FAIL _______ A6 (COMMAND/DATA) ___ _________ LMC, A13(BRDCST/OWN ADDRS), _ A12(T/R),A11-A7(SA4-SA0) PREVIOUS COMMAND A5-A1 (WC/MC4-0, CWC4-0) PREVIOUS COMMAND _____ INCMD ___ WRT (NOTE 1) _____ _____ _____ DTREQ, DTGRT, DTACK, __ DATA15-0, CS (NOTE 1) _______ _______ ILLEGAL, SERVREQ, ____ ______ SSFLAG, BUSY ___ GBR ______ RTFAIL FIGURE 8. BC TO RT (RECEIVE) MESSAGE ERROR TIMING SYMBOL DESCRIPTION MIN TYP MAX UNITS t1(@12MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT 0.97 1.56 s t1(@16MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT 0.87 1.38 s t2(@12MHz) NBGRT PULSE WIDTH 140 190 ns t2(@16MHz) NBGRT PULSE WIDTH 100 150 ns t3 NBGRT RISING EDGE TO A6 FALLING EDGE 45 ns t4(@12MHz) NBGRT FALLING EDGE TO ADDRESS VALID, LMC 300 410 ns t4(@16MHz) NBGRT FALLING EDGE TO VALID ADDRESS, LMC 220 330 ns t5(@12MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 800 865 ns t5(@16MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 590 655 ns t6(@12MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE 1.19 1.28 s t6(@16MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE (Note 2) 0.88 See Note 0.974 s t7 NBGRT FALLING EDGE TO VALID STATUS INPUTS t8 INCMD FALLING EDGE TO CWC VALID t9 DATA TRANSFER CYCLE TIME (Notes 2,3,4) Data Device Corporation www.ddc-web.com 4.1 5 20 60 s ns BU-65153 Rev H-07/07-0 MID-PARITY Y DATA DATA (PARITY ERROR) t2 t11 t12 t3 t4 PRESENT COMMAND t14 WC WC CWC=0 t8 t5 t13 t6 t9 t7 t10 FIGURE 8. BC TO RT (RECEIVE) MESSAGE ERROR TIMING SYMBOL DESCRIPTION MIN TYP MAX UNITS t10 STATUS INPUTS HOLD TIME 500 t11(@12MHz) MID-PARITY CROSSING OF DATA WORD WITH EVEN PARITY TO FALLING EDGE OF ME 5.95 6.26 ms ns t11(@16MHz) MID-PARITY CROSSING OF DATA WORD WITH EVEN PARITY TO FALLING EDGE OF ME 5.87 6.245 s t12 ME FALLING EDGE TO A6 HIGH 45 ns t13(@12MHz) ME FALLING EDGE TO INCMD RISING EDGE 300 360 ns t13(@16MHz) ME FALLING EDGE TO INCMD RISING EDGE 220 280 ns t14 INCMD RISING EDGE TO WORD COUNT VALID 75 ns Notes: 1)IF ADDR_ENA IS LOGIC "1", CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED (DT_ACK = LOGIC "0"). 2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCE t6 IS DEFINED AS THE FALLING EDGE OF DT_REQ. 3)THE TRAILING EDGE OF REFERENCE t9 IS DEFINED AS THE RISING EDGE OF DT_REQ. 4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES. Data Device Corporation www.ddc-web.com 21 BU-65153 Rev H -07/07-0 MID-PARITY RECEIVE COMMAND 1553 BUS TRANSMIT COMMAND t1 _____ NBGRT t2 __ ME _______ HS_FAIL t3 t11 _______ A6 (COMMAND/DATA) t4 ___ _________ LMC, A13(BRDCST/OWN ADDRS), _ A12(T/R),A11-A7(SA4-SA0) PREVIOUS COMMAND A5-A1 (WC/MC4-0, CWC4-0) PREVIOUS COMMAND PRESENT COMMAND WC t5 _____ INCMD CWC=0 t8 ___ WRT (NOTE 1) t6 _____ _____ _____ DTREQ, DTGRT, DTACK, __ DATA15-0, CS (NOTE 1) _______ _______ ILLEGAL, SERVREQ, ______ ____ SSFLAG, BUSY ___ GBR t9 t7 t10 ______ RTFAIL FIGURE 9. RT TO RT (RECEIVE) TIMEOUT TIMING SYMBOL DESCRIPTION MIN TYP MAX UNITS t1(@12MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT 0.97 1.56 ms t1(@16MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT 0.87 1.38 ms t2(@12MHz) NBGRT PULSE WIDTH 140 190 ns t2(@16MHz) NBGRT PULSE WIDTH 100 150 ns t3 NBGRT RISING EDGE TO A6 FALLING EDGE 45 ns t4(@12MHz) NBGRT FALLING EDGE TO ADDRESS VALID, LMC 300 410 ns t4(@16MHz) NBGRT FALLING EDGE TO VALID ADDRESS, LMC 220 330 ns t5(@12MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 800 865 ns t5(@16MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE 590 655 ns t6(@12MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE 1.19 1.28 ms t6(@16MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE (Note 2) 0.88 0.97 ms t7 NBGRT FALLING EDGE TO VALID STATUS INPUTS 4.1 ms t8 INCMD FALLING EDGE TO CWC VALID t9 DATA TRANSFER CYCLE TIME (Notes 2,3,4) Data Device Corporation www.ddc-web.com 5 60 See Note 4 22 BU-65153 Rev H-07/07-0 t12 STATUS DATA t14 WC t13 FIGURE 9. RT TO RT (RECEIVE) TIMEOUT TIMING (CONTINUED) SYMBOL DESCRIPTION MIN TYP MAX UNITS t10 STATUS INPUTS HOLD TIME 500 t11(@12MHz) A6 PULSE WIDTH 820 1205 ns ns t11(@16MHz) A6 PULSE WIDTH 720 1025 ns t12 RT-RT NO RESPONSE TIMEOUT (MESSAGE ERROR) 18.25 19.5 ms t13(@12MHz) ME FALLING EDGE TO INCMD RISING EDGE 300 360 ns t13(@16MHz) ME FALLING EDGE TO INCMD RISING EDGE 220 280 ns t14 INCMD RISING EDGE TO WORD COUNT VALID 75 ns Notes: 1)IF ADDR_ENA IS LOGIC "1", CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED (DT_ACK = LOGIC "0"). 2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCE t6 IS DEFINED AS THE FALLING EDGE OF DT_REQ. 3)THE TRAILING EDGE OF REFERENCE t9 IS DEFINED AS THE RISING EDGE OF DT_REQ. 4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES. Data Device Corporation www.ddc-web.com 23 BU-65153 Rev H -07/07-0 ; ;; ;; ;;; ;;; ;;; DT_REQ t1 t2 DT_GRT t3 t4 DT_ACK WR (SEE NOTE 1) t11 A05-A01 t6 t8 CS (SEE NOTE 1) t7 t9 DB15-DB00 (OUTPUT) valid t10 t5 ADDR. WINDOW (SEE NOTE 1) t12 valid FIGURE 10. DMA WRITE 16-BIT SYMBOL DESCRIPTION MIN TYP MAX UNITS t1(@12MHz) DMA REQUEST TO DMA GRANT (COMMAND WORD) 3.0 s t1(@16MHz) DMA REQUEST TO DMA GRANT (COMMAND WORD) 3.3 s t1(@12MHz) DMA REQUEST TO DMA GRANT (DATA WORD) 3.5 s t1(@16MHz) DMA REQUEST TO DMA GRANT (DATA WORD) 3.7 s t2 DMA GRANT PULSE WIDTH t3 DMA GRANT DELAY TO DMA ACKNOWLEDGE t4 DT_ACK PULSE WIDTH t5 DT_ACK LOW DELAY TO ADDRESS ENABLED (Note 1) t6(@12MHz) DT_ACK LOW DELAY TO RISING EDGE OF CS t6(@16MHz) DT_ACK LOW DELAY TO RISING EDGE OF CS t7(@12MHz) DATA VALID SETUP TIME TO RISING EDGE OF CS 195 t7(@16MHz) DATA VALID SETUP TIME TO RISING EDGE OF CS 255 t8(@12MHz) CS LOW PULSE WIDTH 150 185 ns t8(@16MHz) CS LOW PULSE WIDTH 170 205 ns t9(@12MHz) DATA HOLD TIME FOLLOWING RISING EDGE OF CS 70 ns t9(@16MHz) DATA HOLD TIME FOLLOWING RISING EDGE OF CS 50 ns t10 DATA TRI-STATE SETUP TIME PRIOR TO RISING EDGE OF DT_REQ, DT_ACK 10 ns t11 DT_REQ HIGH DELAY TO ADDRESS UPDATE (Note 1) 60 ns t12 DT_ACK HIGH DELAY TO ADDRESS, WRT, CS TRI-STATE (Note 1) 45 ns 130 ns 130 ns 515 ns 35 ns 315 365 ns 360 410 ns 485 ns ns Note: 1)Diagram assumes ADDR_ENA is set to logic "0". If is was set to logic "1", then A13-A00, CS, and WRT would normally be high impedance until activated by DT_ACK as shown by "ADDR. WINDOW" timing. Data Device Corporation www.ddc-web.com 24 BU-65153 Rev H-07/07-0 ; ;; ; ; ; ;; ;; ;; ;; ; ; DT_REQ t1 t2 DT_GRT t3 t4 DT_ACK WR (SEE NOTE 1) t10 A05-A01 t5 ; ;; ; t8 CS (SEE NOTE 1) t7 ADDRESS WINDOW (SEE NOTE 1) t9 valid DB15-DB00 t6 t11 valid FIGURE 11. DMA READ 16-BIT SYMBOL DESCRIPTION MIN TYP MAX UNITS t1(@12MHz) DMA REQUEST TO DMA GRANT 15.1 s t1(@16MHz) DMA REQUEST TO DMA GRAN) 15.3 s t2 DMA GRANT PULSE WIDTH t3 DMA GRANT DELAY TO DMA ACKNOWLEDGE t4 DT_ACK PULSE WIDTH t5(@12MHz) 130 ns 130 ns 485 515 ns DT_ACK LOW DELAY TO CS LOW 70 115 ns t5(@16MHz) DT_ACK LOW DELAY TO CS LOW 50 95 ns t6 DT_ACK LOW DELAY TO ADDRESS, WRT, CS, ENABLED (Note 1 35 ns t7(@12MHz) DATA VALID SETUP TIME TO RISING EDGE OF CS 180 ns t7(@16MHz) DATA VALID SETUP TIME TO RISING EDGE OF CS 240 ns t8(@12MHz) CS LOW PULSE WIDTH 315 345 ns t8(@16MHz) CS LOW PULSE WIDTH 360 390 ns t9(@12MHz) DATA HOLD TIME FOLLOWING CS HIGH t10 DT_REQ HIGH DELAY TO ADDRESS UPDATE (Note 1) 60 ns 112 DT_ACK HIGH DELAY TO ADDRESS, WRT, CS TRI-STATE (Note 1) 45 ns 0 ns Note: 1)Diagram assumes ADDR_ENA is set to logic "0"" If is was set to logic "1", then A13-A00, CS, and WRT would normally be high impedance until activated by DT_ACK as shown by "ADDRESS WINDOW" timing. Data Device Corporation www.ddc-web.com 25 BU-65153 Rev H -07/07-0 ; ;; ;; ;; ;; ; DT_REQ t1 DT_GRT t2 t3 t4 DT_ACK WR (SEE NOTE 1) t13 A05-A01 t5 A00 t6 t6 CS (SEE NOTE 1) t10 t10 t9 DB15-DB00 (OUTPUT) t9 t11 valid UPPER BYTE t17 (15..8) t12 t11 valid LOWER BYTE t17 (7..0) t12 t14 t8 ADDR. WINDOW (SEE NOTE 1) valid FIGURE 12. DMA WRITE 8-BIT SYMBOL DESCRIPTION MIN TYP MAX UNITS t1(@12MHz) DMA REQUEST TO DMA GRANT (COMMAND WORD) 3.0 s t1(@16MHz) DMA REQUEST TO DMA GRANT (COMMAND WORD) 3.3 s t1(@12MHz) DMA REQUEST TO DMA GRANT (DATA WORD) 3.5 s t1(@16MHz) DMA REQUEST TO DMA GRANT (DATA WORD) 3.7 s t2 DMA GRANT PULSE WIDTH t3 DMA GRANT DELAY TO DMA ACKNOWLEDGE t4 DT_ACK PULSE WIDTH t5 t6(@12MHz) 130 ns 130 ns 985 1015 ns DT_ACK LOW DELAY TO A0 LOW (UPPER BYTE TRANSFER CYCLE TIME 485 515 ns START OF BYTE TRANSFER CYCLETO RISING EDGE OF CS 315 365 ns t6(@16MHz) START OF BYTE TRANSFER CYCLETO RISING EDGE OF CS 360 410 t7 DATA TRI-STATE HOLD TIME FOLLOWING START OF BYTE TRANSFER 50 ???ns t8 DT_ACK LOW DELAY TO ADDRESS, WRT, CS ENABLED (Note 1) 35 ???ns t9(@12MHz) DATA SETUP TIME PRIOR TO RISING EDGE OF CS 195 ns t9(@16MHz) DATA SETUP TIME PRIOR TO RISING EDGE OF CS 255 ns t10(@12MHz) CS PULSE WIDTH 150 ns t10(@16MHz) CS PULSE WIDTH 170 ns t11(@12MHz) DATA HOLD TIME FOLLOWING RISING EDGE OF CS 70 ns t11(@16MHz) DATA HOLD TIME FOLLOWING RISING EDGE OF CS 50 ns t12 DATA TRI-STATE SETUP TIME PRIOR TO END OF BYTE TRANSFER CYCLE 10 t13 DT_REQ HIGH DELAY TO ADDRESS UPDATE (Note 1) 60 ns t14 DT_ACK HIGH DELAY TO ADDRESS, WRT, CS HIGH IMPEDANCE (Note 1) 45 ns ns ns Note: 1)Diagram assumes ADDR_ENA is set to logic "0". If is was set to logic "1", then A13-A00, CS, and WRT would normally be high impedance until activated by DT_ACK as shown by "ADDR. WINDOW" timing. Data Device Corporation www.ddc-web.com 26 BU-65153 Rev H-07/07-0 ; ;; ;; ;; ;; DT_REQ t1 DT_GRT t2 t3 t4 DT_ACK WR (SEE NOTE 1) t11 A05-A01 t5 A00 t6 t6 t3 ; ;; ;; ;; t8 ; ;; CS (SEE NOTE 1) t9 t9 t10 DB15-DB00 (OUTPUT) t7 ADDR. WINDOW (SEE NOTE 1) valid UPPER BYTE (15..8) t10 valid LOWER BYTE (7..0) valid FIGURE 13. DMA READ 8-BIT SYMBOL DESCRIPTION MIN TYP MAX UNITS t1(@12MHz) DMA REQUEST TO DMA GRANT 15.1 s t1(@16MHz) DMA REQUEST TO DMA GRAN) 15.3 s t2 DMA GRANT PULSE WIDTH t3 DMA GRANT DELAY TO DMA ACKNOWLEDGE 130 ns t4 DT_ACK PULSE WIDTHACK PULSE WIDTH 985 1015 ns t5 DT_ACK DELAY TO A0 LOW (UPPER BYTE TRANSFER CYCLE TIME) 485 515 ns t6(@12MHz) START OF BYTE TRANSFER CYCLE TO FALLING EDGE OF CS 70 115 ns t6(@16MHz) START OF BYTE TRANSFER CYCLE TO FALLING EDGE OF CS 50 95 ns t7 DT_ACK LOW DELAY TO ADDRESS, WRT, CS ENABLED (Note 1) 35 ns t8(@12MHz) CS PULSE WIDTH 315 345 ns t8(@16MHz) CS PULSE WIDTH 360 390 ns t10 DATA HOLD TIME FOLLOWING CS HIGH t11 DT_REQ HIGH DELAY TO ADDRESS UPDATE (Note 1) 60 ns 112 DT_ACK HIGH DELAY TO ADDRESS, WRT, CS TRI-STATE (Note 1) 45 ns 130 ns 0 ns Note: 1)Diagram assumes ADDR_ENA is set to logic "0". If is was set to logic "1", then A13-A00, CS, and WRT would normally be high impedance until activated by DT_ACK as shown by "ADDR. WINDOW" timing Data Device Corporation www.ddc-web.com 27 BU-65153 Rev H -07/07-0 t1 ______ DT_REQ t2 ______ DT_GRT t3 _______ HS_FAIL t4 A05 - A01 (NOTE 1) t5 ___ WRT (NOTES 1,2) FIGURE 14. DMA HANDSHAKE FAILURE SYMBOL TRANSFER DESCRIPTION MIN TYP MAX UNITS t1(@12MHz) COMMAND WORD WRITE DT_REQ PULSE WIDTH 3.2 3.3 s t1(@16MHz) COMMAND WORD WRITE DT_REQ PULSE WIDTH 3.5 3.6 s t1(@12MHz) DATA WORD WRITE DT_REQ PULSE WIDTH 3.7 3.8 s t1(@16MHz) DATA WORD WRITE DT_REQ PULSE WIDTH 3.9 4.0 s t1(@12MHz) DATA WORD WRITE DT_REQ PULSE WIDTH 15.3 s t1(@16MHz) DATA WORD WRITE 15.5 s t2 ALL DT_GRT HIGH HOLD TIME FROM DT_REQ RISING t3 ALL HS_FAIL FALLING EDGE FROM DT_REQ RISING EDGE 25 ns t4 ALL WORD COUNT VALID FROM DT_REQ RISING EDGE 60 ns t6(@12MHz) DATA WORD READ DT_REQ RISING EDGE TO WRT LOW 300 400 ns t6(@16MHz) DATA WORD READ DT_REQ RISING EDGE TO WRT LOW 220 310 ns DT_REQ PULSE WIDTH -60 ns Notes: 1)Diagram assumes ADDR_ENA is set to logic "0". If it was set to logic "1" then A13-A00, CS and WRT would normally be in high impedance until activated by DT_ACK as shown by "ADDR. WINDOW" timing. 2)If the transfer requested was a read operation, and a handshake failure occurred, then the WRT signal would return to the write state and the BUS-65153's transmission of the 1553 Bus would terminate at the conclusion of the preset word. Data Device Corporation www.ddc-web.com 28 BU-65153 Rev H-07/07-0 Zo (70 to 85 ) DIRECT COUPLED (SHORT STUB) 1.4:1 31 Vpp 55 ohm 44 Vpp 1 BUS-65153 8 2 BUS-65163 3 1 FT MAX 4 55 ohm ISOLATION TRANSFORMER OR 44 Vpp TRANSFORMER COUPLED (LONG STUB) 2:1 1:1.4 22 Vpp 1 7 31Vpp 8 1 4 3 0.75Zo 2 3 5 20 FT MAX COUPLING TRANSFORMER ISOLATION TRANSFORMER 0.75Zo DIRECT COUPLED (SHORT STUB) 1:0.83(or 1:0.80) 28 Vpp 33 Vpp 1 BUS-65154 8 55 ohm 2 BUS-65164 3 1 FT MAX 4 55 ohm ISOLATION TRANSFORMER OR 33 Vpp TRANSFORMER COUPLED (LONG STUB) 1:0.6 1:1.4 20 Vpp 1 7 28 Vpp 8 1 4 3 0.75Zo 2 3 5 20 FT MAX ISOLATION TRANSFORMER COUPLING TRANSFORMER 0.75Zo Zo (70 to 85 ) FIGURE 15. BUS-65153 AND BUS-65154 TO MIL-STD-1553 INTERFACE Notes for TABLE 4: (1)Shown for one of two redundant buses that interface to the BUS65153 hybrid. (2)Transmitted voltage level on 1553 bus is 6 Vp-p min, 7 Vp-p nominal, 9 Vp-p max. (3)Required tolerance on isolation resistors is 2%. Instantaneous power dissipation (when transmitting) is approximately 0.5 W (typ), 0.8 W (max). (4)Transformer pin numbering is correct for DDC BUS-25679 or BUS29854 transformer. For the Beta transformer (e.g., B-2203) or the QPL21038-31 transformer (e.g., M21038/27-02), the winding sense and turns ratio are mechanically the same, but the pin numbering is reversed. Therefore, it is necessary to reverse pins 8 and 4 or pins 7 and 5 in the diagram for the Beta or QPL transformers. (5) The B-2204, B-2388, and B-2344 transformers have a slightly different turns ratio on the direct coupled taps then the turns ratio of the BUS-29854 direct coupled taps. They do, however, have the same transformer coupled ratio. For transformer coupled applications, either transformer may be used. The transceiver in the BU-65170X2 and the BU-61580X2 was designed to work with a 1:0.83 ratio for direct coupled applications. For direct coupled applications, the 1.20:1 turns ratio is recommended, but the 1.25:1 may be used. The 1.25:1 turns ratio will result in a slightly lower transmitter amplitude. (Approximately 3.6% lower) and a slight shift in the ACE's receiver threshold. INTERFACE TO MIL-STD-1553 BUS Interfacing the BUS-65153 to a MIL-STD-1553 bus requires a pair of pulse transformers. These transformers, or QPL equivalents, are available from Beta Transformer Technology Corporation, a subsidiary of DDC. The BUS-65153 hybrid and Beta Transformers may be wired for either direct coupled or stub coupled configurations. The recommended transformer for each of the BUS-65153 transceiver options is listed in TABLE 4. The interface between a BUS-65153 and a MIL-STD-1553 bus is illustrated in FIGURE 15.Notes for TABLE 4: TABLE 4. RECOMMENDED BETA TRANSFORMEER DEVICE TRANSFORMER BUS-65153/63 BUS-25679, B-2203, LPB-5002 LPB-5009, or M21038/27-02 BUS-65154/64 Data Device Corporation www.ddc-web.com BUS-29854, B-2204 LPB-5001, LPB-5008 or M21038/27-03 29 BU-65153 Rev H -07/07-0 SIMPLE SYSTEM INTERFACE DMA INTERFACE FIGURE 16 illustrates the capability of the STIC to operate in a system with no host processor. A simple linear addressing scheme is used that can be easily decoded to form read and write signals for direct access to data buffers or data latches. A double buffered mechanism may be used on received data in order to maintain data validity and consistency. The STIC may be interfaced to a host processor by means of a simple DMA interface. The address and control lines may be placed in a three-state mode by setting the ADDR_ENA signal to logic "1". While the STIC is not accessing the RAM (i.e., DT_ACK is logic "1") the address, data, and control lines (CS, WRT) are held in a high impedance state. The signals CS and WRT require pull-up resistors. The latched discrete outputs section of the drawing uses two sets of latches. The first latch is updated when the received data word is transferred from the STIC. The second latch is not updated until the message is validated, as indicated by the signal Good Block Received (GBR). If an error, such as parity or Manchester, occurs on a received data word, all the data associated with that message will be ignored, thus fulfilling the data validity/consistancy requirement. The STIC may be programmed to operate in either a 16-bit transfer mode (FIGURE 17) or an 8-bit transfer mode (FIGURE 18). In 16-bit mode (DB_SEL set to logic "0") the signal A0 is not used (always logic "1") and 16-bit transfers are performed on data lines D0..D15. In 8-bit mode (DB_SEL set to logic "1") the signal A0 is used to indicate whether the upper (MSB) data byte (A0 set to logic "1") or the lower (LSB) data byte (A0 set to logic "0") is being transferred. The upper and lower data bytes are not multiplexed internally, therefore, the signals must be connected externally. D0 must be connected to D8, D1 must be connected to D9, ... , and D7 must be connected to D15. WRITE ADDRESS DECODER LATCH LATCH D Q D Q W0 Vcc A0..A13 D Q _ Q WN __ CS LATCHED DISCRETE OUTPUTS BUS LATCH LATCH D Q D Q Vcc 65153 "STIC" D Q _ Q _____ NBGRT ___ GBR TRI-STATE BUFFER READ ADDRESS DECODER BUFFERED R0 DISCRETE RN TRI-STATE BUFFER INPUTS DB0..DB15 ______ DB GRT FIGURE 16. BUS-65153 MINIMUM COMPLEXITY SYSTEM Data Device Corporation www.ddc-web.com 30 BU-65153 Rev H-07/07-0 _______ RX/TX A RX/TX B D0..D7 DB0..DB07 Vcc DB8..DB15 __ ME _______ RT FAIL _______ HS FAIL __________ RT_ADD_ERR _____ INCMD ___ GBR _____ NBGRT RT AD 4 RT AD 3 BUS-65153 RT AD 1 RT AD 0 A00..A13 A00..A13 _______ RX/TX B RT AD 2 ___________ BUS REQUEST _________ BUS GRANT _______________ BUS ACKNOWLEDGE ______ DT REQ ______ DT GNT ______ DT ACK RX/TX A "STIC" A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 RT AD P RT AD LATCH Vcc ______ TX INH ________ ADDR_ENA A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 HOST PROCESSOR CS WE OE Vcc DB_SEL 16Kx8 RAM CLOCK SEL 12 MHZ OSC Vcc ___________ DATA STROBE __ CS CLOCK IN _______ SERVREQ ______ SSFLAG ____ BUSY _______ ILLEGAL _____ RESET _____ READ/WRITE ___ WRT FIGURE 17. BUS-65153 16-BIT DMA INTERFACE RX/TX A _______ RX/TX A RX/TX B ______ DT REQ ______ DT GNT ______ DT ACK _____________ BUS REQUEST ___________ BUS GRANT ___________________ BUS ACKNOWLEDGE A01..A13 A1..A13 D0..D15 DB0..DB15 _______ RX/TX B A00 Vcc RT AD 4 RT AD 3 RT AD 2 RT AD 1 RT AD 0 BUS-65153 "STIC" A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 __________ RT_ADD_ERR __ ME _______ RT FAIL _______ HS FAIL _____ INCMD ___ GBR _____ NBGRT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 RT AD P CS WE OE RT AD LATCH Vcc Vcc Vcc ______ TX INH ________ ADDR_ENA DB_SEL _______ SERVREQ ______ SSFLAG ____ BUSY _______ ILLEGAL _____ RESET D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 HOST PROCESSOR 8Kx16 RAM __ CS ___ WRT _____________ DATA STROBE _____ READ/WRITE Vcc CLOCK SEL 12 MHz CLOCK IN OSC FIGURE 18. BUS-65153 8-BIT DMA INTERFACE Data Device Corporation www.ddc-web.com 31 BU-65153 Rev H -07/07-0 P.C. BOARD LAYOUT GUIDELINES return path is through the transformer center tap and not through the STIC's GND pin. GROUND PLANES It is an important layout consideration to minimize the power supply distribution impedance along this path. Any resistance will result in voltage drops for the power supply input voltage, and can ultimately lower the transmitter output voltage, possibly below the minimum level required by MIL-STD-1553. As is the rule in all high speed digital circuits, it is good practice to use ground and power supply planes under the STIC hybrid as well as the associated components. IT IS VERY IMPORTANT THAT THERE BE NO GROUND AND/OR POWER SUPPLY PLANES UNDERNEATH ANY OF THE ANALOG BUS SIGNAL TRACESTHIS APPLIES TO THE TX/RX SIGNALS RUNNING FROM THE STIC HYBRID TO THE TRANSFORMERS AS WELL AS FROM THE TRANSFORMERS TO ANY CONNECTORS OR CABLES LEAVING THE BOARD 1553 BUS CONNECTIONS The isolation transformers should be placed as physically close as possible to the respective TX/RX pins on the STIC and the distance from the isolation transformers to any connectors or cables leaving the board should be as short as possible. In addition to limiting the voltage drops in the analog signal traces when transmitting, reducing the hybrid-to-transformer and transformer-to-connector spacings serves to minimize crosstalk from other signals on the board. The reason for not using supply or ground planes under the analog signal traces is that the effect of the distributed capacitance will be to lower the input impedance of the terminal, as seen from the 1553 bus. MIL-STD-1553 requires a minimum input impedance of 2000 ohms for direct coupled terminals and 1000 ohms for transformer (stub) coupled terminals. If there are ground planes under the analog bus signal traces, it is likely that the terminal will not meet this requirement. The general practice in connecting the stub side of a transformer (or direct) coupled terminal to an external system connector is to make use of 78 ohm twisted-pair shielded cable. This minimizes impedance discontinuities. The decision of whether to isolate or make connections between the center tap of the isolation transformer's secondary, the stub shield, the bus shield, and/or chassis ground must be made on a system basis, as determined by an analysis of EMI/RFI and lightning considerations. POWER AND GROUND DISTRIBUTION Another important consideration is power and ground distribution. Refer to FIGURE 19. For the STIC hybrid/transformer combination, the high current path when the STIC is transmitting will be from the -15 volt power supply, through the transmitter output stage, through one leg of the isolation transformer to the transformer center tap. It is important to realize that the high current In most systems, it is specified that the 1553 terminal's input impedance must be measured at the system connector. This is -15 V/-12 V (A/B) +5 V LOGIC +5 V A/B HIGH LEVEL CURRENTS BUS-25679 BUS-29854 BUS-41429 1 7 TX 2 TRANSCEIVER LOGIC 8 RX 6 5 LOW LEVEL CURRENTS 3 LOGIC GND GND A/B 4 LOW LEVEL CURRENTS FIGURE 19. POWER/GROUND CURRENT DISTRIBUTION Data Device Corporation www.ddc-web.com 32 BU-65153 Rev H-07/07-0 "SIMULATED BUS" (LAB BENCH) INTERCONNECTIONS despite the fact that the MIL-STD-1553B requirement is for it to be measured looking directly in from the bus side of the isolation transformer. For purposes of software development and system integration, it is generally not necessary to integrate the required couplers, terminators, etc., that comprise a complete MIL-STD-1553B bus. In most instances, a simplified electrical configuration will suffice. The three connection methods illustrated in FIGURE 20 allow the STIC to be interfaced over a (c)simulated bus to simulation and test equipment. It is important to note that the termination resistors indicated are necessary in order to ensure reliable communications between the STIC and the simulation/test equipment. The effect of a relatively long stub cable will be to reduce the measured impedance. In order to keep the impedance above the required level of 1000 ohms (for transformer-coupled stubs), the length of any cable between the 1553 RT and the system connector should be minimized. ISOLATION TRANSFORMER 1 STUB COUPLING 8 STUB COUPLING 7 STIC HYBRID 2 5 3 TEST/ SIMULATION EQUIPMENT 78 1.5W 4 (A) ISOLATION TRANSFORMER 1 DIRECT COUPLING 8 STIC HYBRID 55 1W 2 3 DIRECT COUPLING 55 TEST/ SIMULATION EQUIPMENT 39 0.5W 4 55 1W 55 (B) ISOLATION TRANSFORMER 1 DIRECT COUPLING 8 STIC HYBRID 20 0.5W 55 1W 2 3 STUB COUPLING TEST/ SIMULATION EQUIPMENT 39 0.5W 4 55 1W 20 0.5W (C) FIGURE 20. "SIMULATED BUS" (LAB BENCH) INTERCONNECTIONS A) DIRECT COUPLED TO DIRECT COUPLED (B) TRANSFORMER COUPLED TO TRANSFORMER COUPLED (C) DIRECT COUPLED TO TRANSFORMER COUPLED Data Device Corporation www.ddc-web.com 33 BU-65153 Rev H -07/07-0 TABLE 5. BUS-65153 PIN DESCRIPTIONS POWER AND GROUND PIN NO NAME I/O DESCRIPTION 18 GND - Analog and Digital Ground 35 +5 VA I Logic and CH. A Transceiver +5V Supply Input 70 +5 VOLTS B I CH.B Transceiver +5V Supply Input 36 -15 (-12) VOLTS I CH. A and CH. B Transceiver -15V (-12V) Supply Input NAME I/O DATA BUS (16) PIN NO 10 DB15 (MSB) I/O 11 DB14 I/O 12 DB13 I/O 13 DB12 I/O 14 DB11 I/O 15 DB10 I/O 16 DB09 I/O 17 DB08 I/O 19 DB07 I/O 20 DB06 I/O 21 DB05 I/O 22 DB04 I/O 23 DB03 I/O 24 DB02 I/O 25 DB01 I/O 26 DB00 (LSB) I/O DESCRIPTION 8/16-bit data bus. DB15 through DB00 may be configured as either a 16-bit or an 8-bit data bus. In the 8-bit mode, DB15 thru DB8 should be connected directly to DB7 thru DB0, respectively (DB15 to DB7, DB14 to DB6 , ... , DB8 to DB0). DB15-DB00 is maintained in a high-impedance state except when the BUS-65153 is performing a data write transfer. In the 8-bit mode, the upper byte is transferred first, followed by the lower byte. (TABLE 5 CONTINUES ON THE NEXT PAGE.) Data Device Corporation www.ddc-web.com 34 BU-65153 Rev H-07/07-0 TABLE 5. BUS-65153 PIN DESCRIPTIONS - CONTINUED ADDRESS BUS (14) PIN NO. NAME I/O DESCRIPTION 50 A13 O Broadcast. Latched output signal that represents the RT Address field of the present Command Word. That is, it was either a broadcast message (all ones in the RT Address Field) or a command addressed explicitly to this terminal (the address field of the command word matches the terminals's RTADD04 to RTADD0 inputs and RTAD4-0, RTADP has an odd parity sum.). It is updated after NBGRT but before INCMD goes active. A logic "1" indicates a broadcast command, a logic "0" indicates a command to the BUS-65153's RT Address. Cleared by RESET. (Note 1) 52 A12 O Transmit/Receive - Latched output signal that represents the latched T/R bit (bit 10) of the present Command Word. It is updated after NBGRT but before INCMD goes active. A logic "1" indicates a transmit command, a logic "0" indicates a receive command. Cleared by RESET. (Note 1) 53 A11 (MSB) O 54 A10 O A11 through A07 : Subaddress [4:0] - These outputs are the latched data from the Subaddress field of the received Command Word. They are updated after NBGRT but before INCMD goes active. They are cleared by RESET. A11 corresponds to SA4 which is the MSB and A07 corresponds to SA0 which is the LSB. (Note 1) 55 A09 O 56 A08 O 57 A07 (LSB) O 58 A06 O Command Word Transfer - Active low level output signal that is asserted when the 1553 Command Word is being transferred to the subsystem over the parallel data bus. A06 is high during all Data Word transfers. (Note 1) 59 A05 (MSB) O 60 A04 O 61 A03 O 62 A02 O 63 A01 (LSB) O A05 through A01 (LSB):Word Count [4:0] / Current Word Count [4:0]. Multiplexed output signals which are defined as follows: these outputs are the latched data from the Word Count field of the received Command Word. They are updated after NBGRT but before INCMD goes active. They are cleared by RESET. For the Command Word transfer (A06 = 0) of a nonmode code Command Word, A05-A00 will be 00000. For a mode code Command Word transfer, A05-A00 will reflect the mode code field of the Command Word. If the present command is not a mode code and INCMD is active then these lines become the output of a current word counter. That is, when INCMD goes active, these outputs go to logic "0" and are then incremented after every Data Word transfer or handshake timeout. For a mode code transfer, the single Data Word is accessed at an address location that is offset by a value of 32 above that of the location for the corresponding Command Word. When INCMD goes inactive, A05A01 become the latched Word Count field again. A5 corresponds to WC4 which is the MSB and A1 corresponds to WC0 which is the LSB. (Note 1) 64 A00 O MSB/LSB - Output signal that is used during 8-bit data transfers to indicate which byte of the present 16-bit word is being transferred. A logic "1" indicates the upper byte (MSB) and a logic "0" indicates the lower byte (LSB). The upper byte is transferred first. If a 16-bit data structure is used (DB_SEL = logic "0"), this bit will always be logic "1" (Note 1) CLOCK, RESET, AND TRANSMITTER INHIBIT (4) PIN NO. NAME I/O DESCRIPTION 51 CLOCK IN I 12 or 16 MHz clock input. 43 CLOCKSEL I Clock Frequency Select. If high, selects 12 MHz clock input. If low, selects a 16 MHz clock input. 45 RESET I Master Reset - Active low input signal (2 clock cycles minimum) used to reset the entire circuit. 49 TXINH I Transmitter Inhibit. A low level on this input disables both 1553 transmitters. Notes: 1. A13 through A0, CS, and WRT will be placed in a high impedance state if ADDR_ENA is high and DTACK is inactive (high). 2. The RT Status Word inputs ILLCMD, SERVREQ, SSFLAG, and BUSY are sampled approximately 5 ms following the mid-parity bit zero crossing of the received Command Word. (TABLE 5 CONTINUES ON THE NEXT PAGE.) Data Device Corporation www.ddc-web.com 35 BU-65153 Rev H -07/07-0 TABLE 5. BUS-65153 PIN DESCRIPTIONS - CONTINUED DMA HANDSHAKE AND TRANSFER CONTROL (8) PIN NO. NAME I/O DESCRIPTION 69 DT_REQ O Data Transfer Request. Active low level output signal used to inform the subsystem that the BUS-65153 needs control of the data bus to perform a transfer. Stays low until DT_GRT is received and the transfer is completed or until a handshake failure timeout has occurred. 1 DT_GRT I Data Transfer Grant. Active low level input signal from the subsystem that, in response to a Data Transfer Request, passes control of the parallel data bus to the BUS-65153. 2 DT_ACK O Data Transfer Acknowledge - Active low level output signal used to inform the subsystem that the BUS-65153 has received DT_GRT in response to DT_REQ. DT_ACK remains active until the transfer is complete. 3 CS O Chip Select - Active low level output pulse present in the middle of every data transfer cycle. When the BUS-65153 is writing data to the subsystem, this signal occurs when the data is valid and should be used to latch the data (recommend using rising edge). When the BUS-65153 is reading data from the subsystem, this signal is used to inform the subsystem when to drive the data bus. (Note 1) 4 WRT O Read/Write - Output signal that controls the direction of the data transfers. The direction is normally outward (write = logic "0") and only turns inward (read = logic "1") when the first Data Word is needed from the subsystem. The output will return low (write) after the transmission of the last data word on the 1553 bus. (Note 1) 6 HS_FAIL O Handshake Failure - Active low level output used to flag the subsystem that DT_GRT was not received in response to DT_REQ in time to perform a data transfer. Latched low and cleared by the next NBGRT or RESET. 7 ADDR_ENA I Address Enable. Active low level input signal used to control the operation of WRT, CS, and address bus A13 through A00. If a logic "0" is applied, the above signals are always active. If a logic "1" is applied, these signals are kept in their high impedance state except for when a data transfer is being performed (DT_ACK = logic "0") 8 DB_SEL I Data Bus Select - Input signal used to select the data bus structure (8- or 16-bit width) Logic "0" selects 16-bit data bus Logic "1" selects 8-bit data bus Note: For 8-bit data bus operation, D15 to D08 should be connected directly to D07 to D00, respectively. INTERFACE TO 1553 PULSE TRANSFORMERS (4) PIN NO. NAME I/O DESCRIPTION 5 RX/TXB I/O Channel B Non-Inverted 1553 Serial Data. 9 RX/TXB I/O Channel B Inverted 1553 Serial Data 40 RX/TXA I/O Channel A Non-Inverted 1553 Serial Data 44 TX/TXA I/O Channel A Inverted 1553 Serial Data RT ADDRESS (8) PIN NO. NAME I/O DESCRIPTION 27 RT_ADD_ERR O Remote Terminal Address Parity Error Output Signal that reflects the parity combination of the RT_AD_[4:0] inputs and RT_AD_P input. High level indicates odd parity, low level indicates even parity. Note, if RT_ADD_ERR is low, then the BUS-65153 will not recognize any valid Command Word directed to its own RT address. 28 RT_ADD_LAT I Remote Terminal Address Latch. When low, the internal RDAD4-0 and RTADP register tracks whatever is applied to the respective input pins. When RT_ADD_LAT is high, the information that was on RTAD4-0 and RTADP the last time that RT_ADD_LAT was low is latched internally. The internal RTAD4-0 and RTADP are cleared to logic 0 when RESET is low. 29 RT_ADD_P I Remote Terminal Address [4:0] - Input signal of the address parity bit. The combination of RT_AD_[0:4], and RT_AD_P must comprise an odd parity sum in order to enable recognition of the terminal's address. 30 RTADD00 (LSB) I Remote Terminal Address inputs. 31 RTADD01 I 31 RTADD02 I 33 RTADD03 I 34 RTADD04 (MSB) I Notes: 1. A13 through A0, CS, and WRT will be placed in a high impedance state if ADDR_ENA is high and DTACK is inactive (high). 2. The RT Status Word inputs ILLCMD, SERVREQ, SSFLAG, and BUSY are sampled approximately 5 ms following the mid-parity bit zero crossing of the received Command Word. (TABLE 5 CONTINUES ON THE NEXT PAGE.) Data Device Corporation www.ddc-web.com 36 BU-65153 Rev H-07/07-0 TABLE 5. BUS-65153 PIN DESCRIPTIONS - CONTINUED RT STATUS WORD INPUTS (4) PIN NO. NAME I/O DESCRIPTION 65 ILLCMD O Illegal Command Input. Active low Input used to illegalize any command. If low when sampled, the Message Error bit (bit 10) in the Status Word will be set. The response to an illegal transmit command will be a Status Word only. The only effect of illegalizing a receive command will to inhibit GBR. An illegalized mode code will not perform the actual mode functions. (Note 2) 66 SERVREQ I Service Request - Input signal used to control the Service Request bit (bit 8) in the Status Word. If low when sampled, the Service Request bit will be set. If high, it will be logic"0". (Note 2) 67 SSFLAG I Subsystem Flag - Input signal used to control the Subsystem Flag bit (bit 2) in the Status Word. If low when sampled, the Subsystem Flag bit will be set. If high, the Subsystem Flag bit will be logic "0". (Note 2) 68 BUSY I Input signal used to control the Busy bit (bit 3) in the Status Word. If low when sampled, the Busy bit will be set. If high, it will be cleared. Note, if the Busy bit is set and the command was a transmit command, only the Status Word would be transmitted. Has no effect on data received following a receive command. (Note 2) MESSAGE TIMING OUTPUT SIGNALS (5) PIN NO. NAME I/O DESCRIPTION 37 GBR O Good Block Received - Low level output pulse (2 clock cycles wide) that is used to flag the subsystem that a valid, legal, nonmode receive command with the correct number of data words has been received without a message error and successfully transferred to the subsystem 38 RTFAIL O Remote Terminal Failure - Latched low level output that goes low if a loopback failure (or transmitter shutdown timeout) has occurred during a transmission cycle. A loopback failure occurs under any of the following conditions: (1) the first transmitted word (Status Word) contains an incorrect RT address field, (2) the received version of any transmitted word is either invalid or contains the incorrect sync type, (3) the received 16-bit data pattern for the last transmitted word does not match that of the transmitted version of the word and/or (4) A transmitter timeout (668 ms) has occurred. Reset by the start of the next transmission cycle (Status Word) or a low level on the RESET input. An RTFAIL condition (low level output on RTFAIL) will cause the Terminal Flag bit in the RT Status Register to be set. When this occurs, the RT Flag Status Word bit will be set in response to the next valid nonbroadcast command. 39 NBGRT O New Bus Grant - Low level output pulse (2 clock cycles wide), that is used to indicate the start of a new protocol sequence in response to the Command Word just received from the 1553 bus. 41 INCMD O In Command - Active low level output signal used to inform the subsystem that the BUS-65153 is presently servicing a command that came in on the 1553 bus. 42 ME O Message Error - Active low level output signal used to flag the subsystem that there was a message error on the 1553 bus communication (word, gap, or word count error). This output goes low upon detecting the error and is reset at the start of the next NBGRT pulse or master reset. If this output goes low, all further command servicing is aborted. FACTORY TEST INPUTS (3) PIN NO. NAME I/O DESCRIPTION 46 FACTORY TEST POINT I Connect to + 5 volts. 47 FACTORY TEST POINT I Connect to + 5 volts. 48 FACTORY TEST POINT I Connect to + 5 volts. Notes: 1. A13 through A0, CS, and WRT will be placed in a high impedance state if ADDR_ENA is high and DTACK is inactive (high). 2. The RT Status Word inputs ILLCMD, SERVREQ, SSFLAG, and BUSY are sampled approximately 5 ms following the mid-parity bit zero crossing of the received Command Word. Data Device Corporation www.ddc-web.com 37 BU-65153 Rev H -07/07-0 TABLE 6. BUS-65153/63 PIN LISTING PIN NAME PIN NAME 1 DT_GRT 36 -15 (-12)VOLTS 2 DT_ACK 37 GBR 3 CS 38 RTFAIL 4 WRT 39 NBGRT 5 RX/TX B 40 RX/TX A 6 HS_FAIL 41 INCMD 7 ADDR_ENA 42 ME 8 DB_SEL 43 CLOCKSEL 9 RX/TX B 44 RX/TX A 10 DB!5 (MSB) 45 RESET 11 DB14 46 FACTORY TEST POINT 12 DB13 47 FACTORY TEST POINT 13 DB12 48 FACTORY TEST POINT 14 DB11 49 TXINH 15 DB10 50 AT3 16 DB09 51 CLOCK IN 17 DB08 52 AT2 18 GND 53 AT11 (MSB) 19 DB07 54 A10 20 DB06 55 A09 21 DB05 56 A08 22 DB04 57 A07 (LSB) 23 DB03 58 A06 24 DB02 59 A05 (MSB) 25 DB01 60 A04 26 DB00 (LSB) 61 A03 27 RT_ADD_ERR 62 A02 28 RT_ADD_LAT 63 A01 (LSB) 29 RT_ADD_P 64 A00 30 RTADD00 (LSB) 65 ILLCMD 31 RTADD01 66 SERVREQ 32 RTADD02 67 SSFLAG 1.900 MAX (48.26) 0.015 0.002 TYP (0.381 0.051) 0.215 (5.46) MAX 70 36 INDEX DENOTES PIN 1 1.000 MAX (25.4) 1 35 0.400 MIN TYP (10.16) 0.010 0.002 TYP (0.254 0.051) 0.050 TYP (1.27) 0.070 0.010 (1.78) 34 EQ SP @ 0.050 = 1.700 (43.18) (1.27) TOL NONCUM PIN NUMBERS FOR REF ONLY TOP VIEW SIDE VIEW NOTES: 1. DIMENSIONS ARE IN INCHES (MILLIMETERS). 2. PACKAGE MATERIAL: ALUMINA (AL2O3). 3. LEAD MATERIAL: KOVAR, PLATED BY 150 MINIMUM NICKEL, PLATED BY 50 MINIMUM GOLD. FIGURE 21. BUS-65153/54 DIP MECHANICAL OUTLINE 0.215 (5.46) MAX 0.180 0.010 TYP (4.57 0.25) 1.900 MAX (48.26) 0.100 (2.54) 36 70 69 37 0.400 (10.16) 0.600 (15.24) BOTTOM VIEW 2 34 35 33 RTADD03 68 BUSY 34 RTADD04 (MSB) 69 DT_REQ 35 + 5 VA 70 + 5 VOLTS B 0.018 0.002 DIA TYP (0.46 0.05) SIDE VIEW 0.100 (2.54) TYP 0.050 (1.27) TYP 1.700 (43.18) INDEX DENOTES PIN 1 1.900 (48.26) MAX 1.000 MAX (25.4) TOP VIEW INDEX DENOTES PIN 1 NOTES: 1. DIMENSIONS ARE IN INCHES (MILLIMETERS). 2. PACKAGE MATERIAL: ALUMINA (AL2O3). 3. LEAD MATERIAL: KOVAR, PLATED BY 150 MINIMUM NICKEL, PLATED BY 50 MINIMUM GOLD. FIGURE 22. BUS-65163/64 FLAT PACK MECHANICAL OUTLINE Data Device Corporation www.ddc-web.com 38 BU-65153 Rev H-07/07-0 ORDERING INFORMATION BUS-651XX-XX0X Supplemental Process Requirements: S = Pre-Cap Source Inspection L = Pull Test Q = Pull Test and Pre-Cap Inspection K = One Lot Date Code W = One Lot Date Code and PreCap Source Y = One Lot Date Code and 100% Pull Test Z = One Lot Date Code, PreCap Source and 100% Pull Test Blank = None of the Above Process Requirements: 0 = Standard DDC Processing, no Burn-In (See table below.) 1 = MIL-PRF-38534 Compliant 2 = B* 3 = MIL-PRF-38534 Compliant with PIND Testing 4 = MIL-PRF-38534 Compliant with Solder Dip 5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip 6 = B* with PIND Testing 7 = B* with Solder Dip 8 = B* with PIND Testing and Solder Dip 9 = Standard DDC Processing with Solder Dip, no Burn-In (See table below.) Temperature Grade/Data Requirements: 1 = -55C to +125C 2 = -40C to +85C 3 = 0C to +70C 4 = -55C to +125C with Variables Test Data 5 = -40C to +85C with Variables Test Data 8 = 0C to +70C with Variables Test Data Power Supply and Packaging 53 = +5 V/-15 V DIP 54 = +5 V/-12 V DIP 63 = +5 V/-15 V Flat Pack 64 = +5 V/-12 V Flat Pack Notes: 1. *Standard DDC Processing with burn-in and full temperature test -- see table below. 2. Also available as DESC P/N 5962-92162-01HXC. 3. This product contains tin-lead solder unless noted otherwise Data Bus Transformers: For BUS-65153/63 use BUS-25679, B-2203, LPB-5002, LPB-5009, or M21038/27-02. For BUS-65154/64 use BUS-29854, B-2204, LPB-5001, LPB-5008, or M21038/27-03. STANDARD DDC PROCESSING MIL-STD-883 TEST Data Device Corporation www.ddc-web.com METHOD(S) CONDITION(S) INSPECTION 2009, 2010, 2017, and 2032 -- SEAL 1014 A and C TEMPERATURE CYCLE 1010 C CONSTANT ACCELERATION 2001 A BURN-IN 1015, Table 1 -- 39 BU-65153 Rev H -07/07-0 The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. Please visit our Web site at www.ddc-web.com for the latest information. 105 Wilbur Place, Bohemia, New York 11716-2426 For Technical Support - 1-800-DDC-5757 ext. 7771 Headquarters, N.Y., U.S.A. -Tel: (631) 567-5600, Fax: (631) 567-7358 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)89-15 00 12-11, Fax: +49-(0)89-15 00 12-22 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com RM (R) I FI REG U ST ERED DATA DEVICE CORPORATION REGISTERED TO ISO 9001:2000 FILE NO. A5976 Rev H -07/07-0 40 PRINTED IN THE U.S.A.