SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
3-State Outputs Drive Bus Lines Directly
D
PNP Inputs Reduce dc Loading on Bus
Lines
D
Hysteresis at Bus Inputs Improves Noise
Margins
D
Typical Propagation Delay Times Port to
Port, 8 ns
TYPE IOL
(SINK
CURRENT)
IOH
(SOURCE
CURRENT)
SN54LS245 12 mA –12 mA
SN74LS245 24 mA –15 mA
description
These octal bus transceivers are designed for
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
The devices allow data transmission from the
A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the
direction-control (DIR) input. The output-enable
(OE) input can disable the device so that the
buses are effectively isolated.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – N Tube SN74LS245N SN74LS245N
SOIC – DW
Tube SN74LS245DW
LS245
0°C to 70°C
SOIC
–
DW
Tape and reel SN74LS245DWR
LS245
SOP – NS Tape and reel SN74LS245NSR 74LS245
SSOP – DB Tape and reel SN74LS245DBR LS245
CDIP – J
Tube SN54LS245J SN54LS245J
–55
°
Cto125
°
C
CDIP
–
J
Tube SNJ54LS245J SNJ54LS245J
–
55°C
to
125°C
CFP – W Tube SNJ54LS245W SNJ54LS245W
LCCC – FK Tube SN54LS245FK SN54LS245FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
B1
B2
B3
B4
B5
A3
A4
A5
A6
A7
A2
A1
DIR
B7
B6 OE
A8
GND
B8 VCC
SN54LS245 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
SN54LS245 ...J OR W PACKAGE
SN74LS245 ... DB, DW, N, OR NS PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUAR Y 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OPERATION
OE DIR
OPERATION
L L B data to A bus
LH A data to B bus
H X Isolation
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
Input
9 kΩNOM
TYPICAL OF ALL OUTPUTS
Output
VCC
50 ΩNOM
logic diagram (positive logic)
DIR
OE
A1
B1
1
2
18
19
To Seven Other Channels
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUAR Y 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
q
JA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54LS245 SN74LS245
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current –12 –15 mA
IOL Low-level output current 12 24 mA
TAOperating free-air temperature –55 125 0 70 °C
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUAR Y 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54LS245 SN74LS245
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V
Hysteresis (VT+ – VT–)A or B VCC = MIN 0.2 0.4 0.2 0.4 V
VOH
High level out
p
ut voltage
VCC = MIN,
IOH = –3 mA 2.4 3.4 2.4 3.4
V
V
OH
High
-
level
output
voltage
IH =
,
VIL = VIL(max) IOH = MAX 2 2
V
VOL
Low level out
p
ut voltage
VCC = MIN,
IOL = 12 mA 0.4 0.4
V
V
OL
Low
-
level
output
voltage
IH =
,
VIL = VIL(max) IOL = 24 mA 0.5
V
IOZH Off-state output current,
high-level voltage applied VCC = MAX,
OE at 2 V VO = 2.7 V 20 20 µA
IOZL Off-state output current,
low-level voltage applied VCC = MAX,
OE at 2 V VO = 0.4 V –200 –200 µA
II
Input current at
p
A or B
VI = 5.5 V 0.1 0.1
mA
I
Imax
mum
npu
voltage DIR or OE
CC =
VI = 7 V 0.1 0.1
mA
IIH High-level input current VCC = MAX, VIH = 2.7 V 20 20 µA
IIL Low-level input current VCC = MAX, VIL = 0.4 V –0.2 –0.2 mA
IOS Short-circuit output current§VCC = MAX –40 –225 40 –225 mA
Total, outputs high 48 70 48 70
ICC Supply current Total, outputs low VCC = MAX Outputs open 62 90 62 90 mA
Outputs at high Z 64 95 64 95
†For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output
C45pF
R 667
W
8 12
ns
tPHL
Pro
p
agation delay time high to low level out
p
ut
C
L =
45
p
F
,
R
L =
667
W
8
12
ns
t
PHL
Propagation
dela
y
time
,
high
-
to
lo
w-
le
v
el
o
u
tp
u
t
8
12
tPZL Output enable time to low level
CL=45
p
F
RL= 667
W
27 40
ns
tPZH Output enable time to high level
C
L =
45
pF
,
R
L =
667
W
25 40
ns
tPLZ Output disable time from low level
CL=5
p
F
RL= 667
W
15 25
ns
tPHZ Output disable time from high level
C
L =
5
pF
,
R
L =
667
W
15 28
ns
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUAR Y 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
W aveform 1
(see Notes C
and D)
W aveform 2
(see Notes C
and D) ≈1.5 V
VOH – 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
tw
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
VOL
VOH
Figure 1. Load Circuits and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8002101VRA ACTIVE CDIP J 20 20 TBD A42 N / A for Pkg Type -55 to 125 5962-8002101VR
A
SNV54LS245J
5962-8002101VSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8002101VS
A
SNV54LS245W
80021012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 80021012A
SNJ54LS
245FK
8002101SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8002101SA
SNJ54LS245W
JM38510/32803B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
32803B2A
JM38510/32803BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
32803BRA
JM38510/32803BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/
32803BSA
M38510/32803B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
32803B2A
M38510/32803BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
32803BRA
M38510/32803BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/
32803BSA
SN54LS245J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS245J
SN74LS245DBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS245
SN74LS245DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS245
SN74LS245DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS245
SN74LS245DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS245
SN74LS245DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS245
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LS245DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS245
SN74LS245DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS245
SN74LS245J OBSOLETE CDIP J 20 TBD Call TI Call TI 0 to 70
SN74LS245N ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS245N
SN74LS245N3 OBSOLETE PDIP N 20 TBD Call TI Call TI 0 to 70
SN74LS245NE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS245N
SN74LS245NSR ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS245
SN74LS245NSRE4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS245
SN74LS245NSRG4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS245
SNJ54LS245FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 80021012A
SNJ54LS
245FK
SNJ54LS245J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS245J
SNJ54LS245W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8002101SA
SNJ54LS245W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LS245, SN54LS245-SP, SN74LS245 :
•Catalog: SN74LS245, SN54LS245
•Military: SN54LS245
•Space: SN54LS245-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LS245DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74LS245DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74LS245NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LS245DBR SSOP DB 20 2000 367.0 367.0 38.0
SN74LS245DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74LS245NSR SO NS 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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