19-5530; Rev 5; 4/12 TION KIT EVALUA BLE IL AVA A 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs The MAX11661-MAX11666 are 12-/10-/8-bit, compact, low-power, successive approximation analog-to-digital converters (ADCs). These high-performance ADCs include a high-dynamic range sample-and-hold and a high-speed serial interface. These ADCs accept a full-scale input from 0V to the power supply or to the reference voltage. The MAX11662/MAX11664/MAX11666 feature dual, single-ended analog inputs connected to the ADC core using a 2:1 MUX. The devices also include a separate supply input for data interface and a dedicated input for reference voltage. In contrast, the single-channel devices generate the reference voltage internally from the power supply. These ADCs operate from a 2.2V to 3.6V supply and consume only 3.3mW. The devices include full powerdown mode and fast wake-up for optimal power management and a high-speed 3-wire serial interface. The 3-wire serial interface directly connects to SPI, QSPIK, and MICROWIRE(R) devices without external logic. Excellent dynamic performance, low voltage, low power, ease of use, and small package size make these converters ideal for portable battery-powered data-acquisition applications, and for other applications that demand low-power consumption and minimal space. These ADCs are available in a 10-pin FMAX(R) package, and a 6-pin SOT23 package. These devices operate over the -40NC to +125NC temperature range. Features S 500ksps Conversion Rate, No Pipeline Delay S 12-/10-/8-Bit Resolution S 1-/2-Channel, Single-Ended Analog Inputs S Low-Noise 73dB SNR S Variable I/O: 1.5V to 3.6V (Dual-Channel Only) Allows the Serial Interface to Connect Directly to 1.5V, 1.8V, 2.5V, or 3V Digital Systems S 2.2V to 3.6V Supply Voltage S Low Power 3.3mW Very Low Power Consumption at 8A/ksps S External Reference Input (Dual-Channel Devices Only) S 1.3A Power-Down Current S SPI-/QSPI-/MICROWIRE-Compatible Serial Interface S 10-Pin, 3mm x 5mm MAX Package S 6-Pin, 2.8mm x 2.9mm SOT23 Package S Wide -40NC to +125NC Operation Applications Data Acquisition Portable Data Logging Medical Instrumentation Battery-Operated Systems Communication Systems Automotive Systems Ordering Information PART PIN-PACKAGE BITS NO. OF CHANNELS MAX11661AUT+ 6 SOT23 8 1 MAX11662AUB+ 10 FMAX-EP* 8 2 MAX11663AUT+ 6 SOT23 10 1 MAX11664AUB+ 10 FMAX-EP* 10 2 MAX11665AUT+ 6 SOT23 12 1 MAX11666AUB+ 10 FMAX-EP* 12 2 MAX11666AUB/V+ 10 FMAX-EP* 12 2 Note: All devices are specified over the -40C to +125C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. /V denotes an automotive qualified part. QSPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. MAX is a registered trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX11661-MAX11666 General Description MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND..............................................................-0.3V to +4V REF, OVDD, AIN1, AIN2, AIN to GND.........-0.3V to the lower of (VDD + 0.3V) and +4V CS, SCLK, CHSEL, DOUT TO GND.............-0.3V to the lower of (VOVDD + 0.3V) and +4V AGND to GND.......................................................-0.3V to +0.3V Input/Output Current (all pins)............................................50mA Continuous Power Dissipation (TA = +70NC) 6-Pin SOT23 (derate 8.7mW/NC above +70NC)............696mW 10-Pin FMAX (derate 8.8mW/NC above +70NC)........707.3mW Operating Temperature Range........................ .-40NC to +125NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (MAX11666) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q1 LSB Q1 LSB Q0.3 Q4 LSB Q1 Q3 LSB DC ACCURACY Resolution 12 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error OE Gain Error GE Total Unadjusted Error TUE Bits No missing codes Excluding offset and reference errors Q1 LSB Channel-to-Channel Offset Matching Q0.4 LSB Channel-to-Channel Gain Matching Q0.05 LSB dB DYNAMIC PERFORMANCE (fAIN = 250kHz) Signal-to-Noise and Distortion SINAD 70 72 Signal-to-Noise Ratio SNR 70.5 72.5 Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Intermodulation Distortion IMD -85 75.5 85 dB -74.5 dB dB f1 = 239.8kHz, f2 = 200.2kHz -84 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 68dB 2.5 MHz Small-Signal Bandwidth 45 MHz Crosstalk -90 dB 2_______________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 500 ksps CONVERSION RATE Throughput 5 Conversion Time 1.56 Acquisition Time tACQ Aperture Delay Fs 52 From CS falling edge ns 4 Aperture Jitter ns 15 Serial-Clock Frequency ps fCLK 0.08 8 MHz VAIN_ 0 VREF V Q1 FA ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance IILA CAIN_ 0.002 Track 20 Hold 4 pF EXTERNAL REFERENCE INPUT (REF) Reference Input Voltage Range Reference Input Leakage Current Reference Input Capacitance VREF IILR 1 Conversion stopped 0.005 CREF VDD + 0.05 V Q1 FA 5 pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage VIH Digital Input Low Voltage VIL Digital Input Hysteresis 0.75 x VOVDD 0.25 x VOVDD 0.15 x VOVDD VHYST Digital Input Leakage Current IIL Digital Input Capacitance CIN V Inputs at GND or VDD 0.001 V V Q1 2 FA pF DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 200FA Output Low Voltage VOL ISINK = 200FA High-Impedance Leakage Current IOL High-Impedance Output Capacitance COUT 0.85 x VOVDD V 4 0.15 x VOVDD V Q1.0 FA pF _______________________________________________________________________________________3 MAX11661-MAX11666 ELECTRICAL CHARACTERISTICS (MAX11666) (continued) MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11666) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (FullPower Mode), No Clock VDD 2.2 3.6 V VOVDD 1.5 VDD V IVDD VAIN_ = VGND 1.67 IOVDD VAIN_ = VGND 0.1 IVDD Power-Down Current IPD Line Rejection 1.5 Leakage only 1.3 VDD = 2.2V to 3.6V, VREF = 2.2V 0.7 mA mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 2) Quiet Time tQ (Note 3) 4 ns CS Pulse Width t1 (Note 3) 10 ns CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled t2 (Note 3) 5 ns t3 (Note 3) 1 ns Figure 2, VOVDD = 2.2V to 3.6V 15 Figure 2, VOVDD = 1.5V to 2.2V 16.5 Data Access Time After SCLK Falling Edge t4 SCLK Pulse Width Low t5 Percentage of clock period (Note 3) 40 60 % SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT High Impedance Power-Up Time t6 Percentage of clock period (Note 3) 40 60 % t7 Figure 3 5 t8 Figure 4 (Note 3) ns ns 2.5 Conversion cycle (Note 3) 14 ns 1 Cycle ELECTRICAL CHARACTERISTICS (MAX11665) (VDD = 2.2V to 3.6V, fSCLK = 8MHz, 50% duty cycle, 500ksps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q1 LSB Q1 LSB Q1.5 Q4 LSB Q1 Q3 LSB DC ACCURACY Resolution 12 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error OE Gain Error GE Total Unadjusted Error TUE Bits No missing codes Excluding offset and reference errors Q1.5 LSB DYNAMIC PERFORMANCE (fAIN = 250kHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio SINAD 70 72.5 dB SNR 70.5 73 dB 4_______________________________________________________________________________________ 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs (VDD = 2.2V to 3.6V, fSCLK = 8MHz, 50% duty cycle, 500ksps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Intermodulation Distortion IMD CONDITIONS MIN 77 TYP MAX UNITS -85 -76 dB 85 dB f1 = 239.8kHz, f2 = 200.2kHz -84 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 68dB 2.5 MHz 45 MHz Small-Signal Bandwidth CONVERSION RATE Throughput 5 Conversion Time Acquisition Time tACQ Aperture Delay ksps Fs 52 ns From CS falling edge Aperture Jitter Serial Clock Frequency 500 1.56 4 ns 15 ps fCLK 0.08 8 MHz Input Voltage Range VAIN 0 VDD V Input Leakage Current IILA Q1 FA ANALOG INPUT Input Capacitance CAIN 0.002 Track 20 Hold 4 pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage VIH Digital Input Low Voltage VIL Digital Input Hysteresis 0.75 x VVDD 0.25 x VVDD 0.15 x VVDD VHYST Digital Input Leakage Current IIL Digital Input Capacitance CIN V Inputs at GND or VDD 0.001 V V Q1 2 FA pF DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 200FA Output Low Voltage VOL ISINK = 200FA High-Impedance Leakage Current IOL High-Impedance Output Capacitance 0.85 x VVDD COUT V 0.15 x VVDD V Q1.0 FA 4 pF POWER SUPPLY Positive Supply Voltage VDD Positive Supply Current (Full-Power Mode) IVDD 2.2 VAIN = VGND 3.6 V 1.76 mA _______________________________________________________________________________________5 MAX11661-MAX11666 ELECTRICAL CHARACTERISTICS (MAX11665) (continued) MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11665) (continued) (VDD = 2.2V to 3.6V, fSCLK = 8MHz, 50% duty cycle, 500ksps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Positive Supply Current (FullPower Mode), No Clock SYMBOL CONDITIONS MIN IVDD Power-Down Current IPD Line Rejection TYP MAX 1.48 Leakage only 1.3 VDD = 2.2V to 3.6V 0.7 UNITS mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 2) Quiet Time tQ (Note 3) 4 ns CS Pulse Width t1 (Note 3) 10 ns CS Fall to SCLK Setup t2 (Note 3) 5 ns CS Falling Until DOUT HighImpedance Disabled t3 (Note 3) 1 ns Data Access Time After SCLK Falling Edge t4 Figure 2, VDD = 2.2V to 3.6V SCLK Pulse Width Low t5 Percentage of clock period (Note 3) SCLK Pulse Width High t6 Percentage of clock period (Note 3) Data Hold Time From SCLK Falling Edge t7 Figure 3 5 SCLK Falling Until DOUT High Impedance t8 Figure 4 (Note 3) Power-Up Time 15 ns 40 60 % 40 60 % ns 2.5 Conversion cycle (Note 3) 14 ns 1 Cycle ELECTRICAL CHARACTERISTICS (MAX11664) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 8MHz, 50% duty cycle, 500ksps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 10 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error OE Gain Error GE Total Unadjusted Error TUE Bits No missing codes Q0.5 0 Excluding offset and reference errors Q0.5 LSB Q0.5 LSB Q1.3 LSB Q1.3 LSB Q0.5 LSB Channel-to-Channel Offset Matching Q0.1 LSB Channel-to-Channel Gain Matching Q0.05 LSB DYNAMIC PERFORMANCE (fAIN = 250kHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio SINAD 60.5 61.6 dB SNR 60.5 61.6 dB Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR -83 75 6_______________________________________________________________________________________ -73 dB dB 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 8MHz, 50% duty cycle, 500ksps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER Intermodulation Distortion SYMBOL IMD CONDITIONS MIN f1 = 239.8kHz, f2 = 200.2kHz TYP MAX UNITS -82 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 60dB 2.5 MHz Small-Signal Bandwidth 45 MHz Crosstalk -90 dB CONVERSION RATE Throughput 5 Conversion Time 500 1.56 Acquisition Time tACQ Aperture Delay Fs 52 ns 4 From CS falling edge Aperture Jitter ns 15 Serial-Clock Frequency ksps ps fCLK 0.08 8 MHz VAIN_ 0 VREF V Q1 FA ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance IILA CAIN-_ 0.002 Track 20 Hold 4 pF EXTERNAL REFERENCE INPUT (REF) Reference Input Voltage Range Reference Input Leakage Current Reference Input Capacitance VREF IILR 1 Conversion stopped 0.005 CREF VDD + 0.05 V Q1 FA 5 pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage VIH Digital Input Low Voltage VIL Digital Input Hysteresis 0.75 x VOVDD 0.25 x VOVDD 0.15 x VOVDD VHYST Digital Input Leakage Current IIL Digital Input Capacitance CIN V Inputs at GND or VDD 0.001 V V Q1 2 FA pF DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 200A Output Low Voltage VOL ISINK = 200A High-Impedance Leakage Current IOL High-Impedance Output Capacitance COUT 0.85 x VOVDD V 4 0.15 x VOVDD V Q1.0 FA pF _______________________________________________________________________________________7 MAX11661-MAX11666 ELECTRICAL CHARACTERISTICS (MAX11664) (continued) MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11664) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 8MHz, 50% duty cycle, 500ksps; CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (Full-Power Mode), No Clock VDD 2.2 3.6 V VOVDD 1.5 VDD V IVDD VAIN_ = VGND 1.67 IOVDD VAIN_ = VGND 0.1 IVDD Power-Down Current IPD Line Rejection 1.5 Leakage only 1.3 VDD = 2.2V to 3.6V, VREF = 2.2V 0.17 mA mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 2) Quiet Time tQ (Note 3) 4 ns CS Pulse Width t1 (Note 3) 10 ns CS Fall to SCLK Setup t2 (Note 3) 5 ns CS Falling Until DOUT HighImpedance Disabled t3 (Note 3) 1 ns Data Access Time After SCLK Falling Edge (Figure 2) t4 SCLK Pulse Width Low t5 Percentage of clock period (Note 3) 40 60 % SCLK Pulse Width High t6 Percentage of clock period (Note 3) 40 60 % Data Hold Time From SCLK Falling Edge t7 Figure 3 5 SCLK Falling Until DOUT High Impedance t8 Figure 4 (Note 3) Power-Up Time VOVDD = 2.2V to 3.6V 15 VOVDD = 1.5V to 2.2V 16.5 ns ns 2.5 Conversion cycle (Note 3) 14 ns 1 Cycle ELECTRICAL CHARACTERISTICS (MAX11663) (VDD = 2.2V to 3.6V. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q0.5 LSB DC ACCURACY Resolution 10 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error OE Gain Error GE Total Unadjusted Error TUE Bits No missing codes Excluding offset and reference errors Q0.5 LSB Q0.3 Q1.3 LSB Q0.15 Q1.3 LSB Q1 8_______________________________________________________________________________________ LSB 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs (VDD = 2.2V to 3.6V. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE (fAIN = 250kHz) Signal-to-Noise and Distortion SINAD 60.5 61.5 Signal-to-Noise Ratio SNR 60.5 61.5 Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Intermodulation Distortion IMD -85 dB dB -73 75 f1 = 239.8kHz, f2 = 200.2kHz dB dB -82 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 60dB 2.5 MHz 45 MHz Small-Signal Bandwidth CONVERSION RATE Throughput 5 Conversion Time 500 1.56 Acquisition Time tACQ Aperture Delay Fs 52 ns 4 From CS falling edge Aperture Jitter ns 15 Serial Clock Frequency ksps ps fCLK 0.08 8 MHz Input Voltage Range VAIN 0 VDD V Input Leakage Current IILA Q1 FA ANALOG INPUT (AIN) Input Capacitance CAIN 0.002 Track 20 Hold 4 pF DIGITAL INPUTS (SCLK, CS, CHSEL) Digital Input High Voltage VIH Digital Input Low Voltage VIL Digital Input Hysteresis 0.75 x VVDD 0.25 x VVDD 0.15 x VVDD VHYST Digital Input Leakage Current IIL Digital Input Capacitance CIN V Inputs at GND or VDD 0.001 2 V V Q1 FA pF _______________________________________________________________________________________9 MAX11661-MAX11666 ELECTRICAL CHARACTERISTICS (MAX11663) (continued) MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11663) (continued) (VDD = 2.2V to 3.6V. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 200A Output Low Voltage VOL ISINK = 200A High-Impedance Leakage Current IOL High-Impedance Output Capacitance 0.85 x VVDD COUT V 0.15 x VVDD V Q1.0 FA 4 pF POWER SUPPLY Positive Supply Voltage VDD Positive Supply Current (Full-Power Mode) IVDD Positive Supply Current (Full-Power Mode), No Clock IVDD Power-Down Current IPD Line Rejection 2.2 VAIN = VGND 3.6 V 1.76 mA 1.48 Leakage only 1.3 VDD = 2.2V to 3.6V 0.17 mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 2) Quiet Time tQ (Note 3) 4 ns CS Pulse Width t1 (Note 3) 10 ns CS Fall to SCLK Setup t2 (Note 3) 5 ns CS Falling Until DOUT HighImpedance Disabled t3 (Note 3) 1 ns Data Access Time After SCLK Falling Edge t4 Figure 2, VDD = 2.2V to 3.6V SCLK Pulse Width Low t5 Percentage of clock period (Note 3) SCLK Pulse Width High t6 Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT High Impedance Power-Up Time 15 ns 40 60 % Percentage of clock period (Note 3) 40 60 % t7 Figure 3 5 t8 Figure 4 (Note 3) 2.5 Conversion cycle (Note 3) 10 ns 14 ns 1 Cycle 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 8MHz, 50% duty cycle, 500ksps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q0.25 LSB DC ACCURACY Resolution 8 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error No missing codes OE Gain Error GE Total Unadjusted Error TUE Bits Excluding offset and reference errors Q0.25 LSB 0.45 Q0.8 LSB 0 Q0.25 LSB 0.5 LSB Channel-to-Channel Offset Matching 0.01 LSB Channel-to-Channel Gain Matching 0.01 LSB DYNAMIC PERFORMANCE (fAIN = 250kHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio SINAD 49 49.7 dB SNR 49 49.7 dB Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Intermodulation Distortion IMD -75 63 -67 67 dB dB f1 = 239.8kHz, f2 = 200.2kHz -65 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 49dB 2.5 MHz Small-Signal Bandwidth 45 MHz Crosstalk -90 dB CONVERSION RATE Throughput 5 Conversion Time 500 1.56 Acquisition Time tACQ Aperture Delay Fs 52 ns 4 From CS falling edge Aperture Jitter ns 15 Serial-Clock Frequency fCLK 0.08 VAIN_ 0 ksps ps 8 MHz ANALOG INPUT (AIN1, AIN2) Input Voltage Range Input Leakage Current Input Capacitance IILA CAIN_ 0.002 Track 20 Hold 4 VREF V Q1 FA pF EXTERNAL REFERENCE INPUT (REF) Reference Input Voltage Range Reference Input Leakage Current Reference Input Capacitance VREF IILR CREF 1 Conversion stopped 0.005 5 VDD + 0.05 V Q1 FA pF ______________________________________________________________________________________11 MAX11661-MAX11666 ELECTRICAL CHARACTERISTICS (MAX11662) MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11662) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 8MHz, 50% duty cycle, 500ksps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, CS) Digital Input High Voltage VIH Digital Input Low Voltage VIL Digital Input Hysteresis 0.75 x VOVDD 0.25 x VOVDD 0.15 x VOVDD VHYST Digital Input Leakage Current IIL Digital Input Capacitance CIN V Inputs at GND or VDD 0.001 V V Q1 2 FA pF DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 200A (Note 3) Output Low Voltage VOL ISINK = 200A (Note 3) High-Impedance Leakage Current High-Impedance Output Capacitance POWER SUPPLY Positive Supply Current (Full-Power Mode) Positive Supply Current (Full-Power Mode), No Clock Power-Down Current V IOL COUT Positive Supply Voltage Digital I/O Supply Voltage 0.85 x VOVDD 0.15 x VOVDD V Q1.0 FA 4 VDD 2.2 VOVDD 1.5 pF 3.6 V VDD V IVDD VAIN_ = VGND 1.67 IOVDD VAIN_ = VGND 0.1 IVDD IPD Line Rejection 1.5 Leakage only 1.3 VDD = 2.2V to 3.6V, VREF = 2.2V 0.17 mA mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 2) Quiet Time tQ (Note 3) 4 ns CS Pulse Width t1 (Note 3) 10 ns CS Fall to SCLK Setup CS Falling Until DOUT HighImpedance Disabled t2 (Note 3) 5 ns t3 (Note 3) 1 ns VOVDD = 2.2V to 3.6V (Note 3) 15 VOVDD = 1.5V to 2.2V (Note 3) 16.5 Data Access Time After SCLK Falling Edge (Figure 2) t4 SCLK Pulse Width Low t5 Percentage of clock period 40 60 % SCLK Pulse Width High Data Hold Time From SCLK Falling Edge SCLK Falling Until DOUT High Impedance Power-Up Time t6 Percentage of clock period 40 60 % t7 Figure 3 5 t8 Figure 4 (Note 3) 2.5 Conversion cycle (Note 3) 12 ns ns 14 ns 1 Cycle 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs (VDD = 2.2V to 3.6V. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error OE Gain Error GE Total Unadjusted Error TUE Bits Q0.25 LSB Q0.25 LSB Q0.45 Q0.8 LSB Q0.04 Q0.5 LSB No missing codes Excluding offset and reference errors Q0.75 LSB dB DYNAMIC PERFORMANCE (fAIN = 250kHz) Signal-to-Noise and Distortion SINAD 49 49.5 Signal-to-Noise Ratio SNR 49 49.5 Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Intermodulation Distortion IMD -70 63 dB -67 66 dB dB f1 = 239.8kHz, f2 = 200.2kHz -65 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 49dB 2.5 MHz 45 MHz Small-Signal Bandwidth CONVERSION RATE Throughput 5 Conversion Time 500 1.56 Acquisition Time tACQ Aperture Delay Aperture Jitter Serial-Clock Frequency Fs 52 From CS falling edge fCLK 0.08 Input Voltage Range VAIN 0 Input Leakage Current IILA Input Capacitance CAIN ksps ns 4 ns 15 ps 8 MHz ANALOG INPUT (AIN) 0.002 Track 20 Hold 4 VDD V Q1 FA pF DIGITAL INPUTS (SCLK, CS) Digital Input High Voltage VIH Digital Input Low Voltage VIL Digital Input Hysteresis 0.75 x VVDD 0.25 x VVDD 0.15 VVDD VHYST Digital Input Leakage Current IIL Digital Input Capacitance CIN V Inputs at GND or VDD 0.001 2 V V Q1 FA pF ______________________________________________________________________________________13 MAX11661-MAX11666 ELECTRICAL CHARACTERISTICS (MAX11661) MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11661) (continued) (VDD = 2.2V to 3.6V. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 200A Output Low Voltage VOL ISINK = 200A High-Impedance Leakage Current IOL High-Impedance Output Capacitance 0.85 x VVDD COUT V 0.15 x VVDD V Q1.0 FA 4 pF POWER SUPPLY Positive Supply Voltage VDD Positive Supply Current (Full-Power Mode) IVDD Positive Supply Current (Full-Power Mode), No Clock IVDD Power-Down Current IPD Line Rejection 2.2 VAIN = VGND 3.6 V 1.76 mA 1.48 Leakage only 1.3 VDD = 2.2V to 3.6V 0.17 mA 10 FA LSB/V TIMING CHARACTERISTICS (Note 2) Quiet Time tQ (Note 3) 4 ns CS Pulse Width t1 (Note 3) 10 ns CS Fall to SCLK Setup t2 (Note 3) 5 ns CS Falling Until DOUT HighImpedance Disabled t3 (Note 3) 1 ns Data Access Time After SCLK Falling Edge t4 Figure 2, VDD = 2.2V to 3.6V SCLK Pulse Width Low t5 Percentage of clock period (Note 3) SCLK Pulse Width High t6 Percentage of clock period (Note 3) Data Hold Time From SCLK Falling Edge t7 Figure 3 5 SCLK Falling Until DOUT High Impedance t8 Figure 4 (Note 3) Power-Up Time 15 ns 40 60 % 40 60 % 2.5 Conversion cycle (Note 3) Note 1: Limits at TA = -40NC are guaranteed by design and not production tested. Note 2: All timing specifications given are with a 10pF capacitor. Note 3: Guaranteed by design in characterization; not production tested. 14 ns 14 ns 1 Cycle 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs SAMPLE t1 t6 CS t5 t2 SCLK DOUT 16 1 2 0 HIGH IMPEDANCE 3 D11 4 D10 5 D9 6 7 D8 D7 8 D6 9 10 D5 D4 11 D3 12 D2 13 D1 14 D0 15 0 0 (MSB) t3 t4 16 t7 1 HIGH IMPEDANCE t8 tQUIET tCONVERT tACQ 1/fSAMPLE Figure 1. Interface Signals for Maximum Throughput, 12-Bit Devices t7 t4 SCLK SCLK VIH DOUT OLD DATA NEW DATA VIL VIH DOUT OLD DATA NEW DATA VIL Figure 3. Hold Time After SCLK Falling Edge Figure 2. Setup Time After SCLK Falling Edge t8 SCLK DOUT HIGH IMPEDANCE Figure 4. SCLK Falling Edge DOUT Three-State ______________________________________________________________________________________15 MAX11661-MAX11666 SAMPLE Typical Operating Characteristics (MAX11665AUT+, TA = +25C, unless otherwise noted.) SOT23 TYPICAL OPERATING CHARACTERISTICS DIFFERENTIAL NONLINEARITY (DNL) vs. OUTPUT CODE -0.5 OFFSET ERROR (LSB) 0 3 MAX11661 toc02 0.5 DNL (LSB) 0.5 OFFSET ERROR vs. TEMPERATURE 1.0 MAX11661 toc01 1.0 0 MAX11661 toc03 INTEGRAL NONLINEARITY (INL) vs. OUTPUT CODE INL (LSB) 2 1 -0.5 -1.0 -1.0 1000 0 2000 3000 4000 0 DIGITAL OUTPUT CODE (DECIMAL) 1000 2000 3000 0 4000 -40 -25 -10 5 20 35 50 65 80 95 110 125 DIGITAL OUTPUT CODE (DECIMAL) TEMPERATURE (C) SIGNAL-TO-NOISE RATIO (SNR) vs. ANALOG INPUT FREQUENCY GAIN ERROR vs. TEMPERATURE MAX11661 toc05 1 74 SNR (dB) GAIN ERROR (LSB) 76 MAX11661 toc04 2 0 72 -1 -2 70 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 50 100 150 200 250 TEMPERATURE (C) fIN (kHz) THD vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE (SFDR) vs. ANALOG INPUT FREQUENCY MAX11661 toc07 95 MAX11661 toc06 -70 93 SFDR (dB) -80 THD (dB) MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs 91 89 -90 87 85 -100 0 50 100 150 fIN (kHz) 200 250 0 50 100 150 fIN (kHz) 16 200 250 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs SOT23 TYPICAL OPERATING CHARACTERISTICS SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) vs. ANALOG INPUT FREQUENCY SINAD (dB) 72 fIN = 99.4kHz fS = 500ksps VDD = 3V -20 MAGNITUDE (dB) 74 MAX11661 toc09 100kHz SINE-WAVE INPUT 0 MAX11661 toc08 76 -40 -60 AHD2 = - 88dB -80 -100 70 -120 50 0 100 150 200 250 50 100 150 200 FREQUENCY (kHz) SUPPLY CURRENT vs. TEMPERATURE SIGNAL-TO-NOISE RATIO (SNR) vs. SUPPLY VOLTAGE (VDD) 74 1.4 SNR (dB) VDD = 3V VDD = 2.2V 1.3 250 MAX11661 toc11 VDD = 3.6V 1.5 75 MAX11661 toc10 1.6 73 72 1.2 71 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.2 2.4 2.6 TEMPERATURE (C) 2.8 3.0 3.2 3.4 3.6 VDD (V) THD vs. INPUT RESISTANCE HISTOGRAM FOR 30,000 CONVERSIONS -75 MAX11661 toc12 35,000 30,000 MAX11661 toc13 IVDD (mA) 0 fIN (kHz) fS = 500ksps fIN = 250kHz -80 THD (dB) CODE COUNT 25,000 20,000 15,000 -85 -90 10,000 -95 5000 -100 0 2046 2047 2048 2049 DIGITAL CODE OUTPUT 2050 0 20 40 60 80 100 RIN (I) ______________________________________________________________________________________17 MAX11661-MAX11666 Typical Operating Characteristics (continued) (MAX11665AUT+, TA = +25C, unless otherwise noted.) 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661-MAX11666 Pin Configurations TOP VIEW AIN1 1 AIN2 2 AGND 3 REF 4 VDD 5 TOP VIEW + MAX11662 MAX11664 MAX11666 EP* 10 SCLK 9 DOUT 8 OVDD 7 CHSEL 6 CS VDD 1 + GND 2 MAX11661 MAX11663 MAX11665 AIN 3 MAX 6 CS 5 DOUT 4 SCLK SOT23 *CONNECT EP TO GROUND PLANE. DEVICES DO NOT OPERATE WHEN EP IS NOT CONNECTED TO GROUND! Pin Description PIN NAME FUNCTION MAX SOT23 1 -- AIN1 Analog Input Channel 1. Single-ended analog input with respect to AGND with range of 0V to VREF. 2 -- AIN2 Analog Input Channel 2. Single-ended analog input with respect to AGND with range of 0V to VREF. -- 3 AIN Analog Input Channel. Single-ended analog input with respect to GND with range of 0V to VDD. -- 2 GND Ground. Connect GND to the GND ground plane. 3 -- AGND 4 -- REF External Reference Input. REF defines the signal range of the input signal AIN1/AIN2: 0V to VREF. The range of VREF is 1V to VDD. Bypass REF to AGND with 10FF || 0.1FF capacitor. 5 1 VDD Positive Supply Voltage. Bypass VDD with a 10FF || 0.1FF capacitor to GND. VDD range is 2.2V to 3.6V. For the SOT23 package, VDD also defines the signal range of the input signal AIN: 0V to VDD. 6 6 CS Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal, starts a conversion, and frames the serial-data transfer. 7 -- CHSEL Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to select AIN1 for conversion. 8 -- OVDD Digital Interface Supply for SCLK, CS, DOUT, and CHSEL. The OVDD range is 1.5V to VDD. Bypass OVDD with a 10FF || 0.1FF capacitor to GND. 9 5 DOUT Three-State Serial-Data Output. ADC conversion results are clocked out on the falling edge of SCLK, MSB first. See Figure 1. 10 4 SCLK Serial-Clock Input. SCLK drives the conversion process. DOUT is updated on the falling edge of SCLK. See Figures 2 and 3. -- -- EP Analog Ground. Connect AGND directly the GND ground plane. Exposed Pad (MAX Only). Connect EP directly to a solid ground plane. Devices do not operate when EP is not connected to ground! 18 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs VDD CS SCLK CONTROL LOGIC SAR OVDD VDD MAX11662 MAX11664 MAX11666 OUTPUT BUFFER CS SCLK DOUT CONTROL LOGIC MAX11661 MAX11663 MAX11665 OUTPUT BUFFER SAR DOUT CHSEL AIN1 AIN2 AIN MUX CDAC CDAC VREF = VDD REF AGND GND (EP) GND Typical Operating Circuit VDD OVDD VOVDD +3V AIN1 ANALOG INPUTS AIN2 MAX11662 MAX11664 MAX11666 AGND SCK CPU DOUT REF +2.5V SCLK CS MISO SS CHSEL GND (EP) VDD +3V GND ANALOG INPUT AIN MAX11661 MAX11663 MAX11665 SCLK SCK DOUT MISO CS CPU SS ______________________________________________________________________________________19 MAX11661-MAX11666 Functional Diagrams MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs Detailed Description throughput rates. The wake-up and power-down feature is controlled by using the SPI interface as described in the Operating Modes section. The MAX11661-MAX11666 are fast, 12-/10-/8-bit, lowpower, single-supply ADCs. The devices operate from a 2.2V to 3.6V supply and consume only 2.98mW (VDD = 2.2V) or 4.37mW (VDD = 3V). These devices are capable of sampling at full rate when driven by an 8MHz clock. The dual-channel devices provide a separate digital supply input (OVDD) to power the digital interface enabling communication with 1.5V, 1.8V, 2.5V, or 3V digital systems. Serial Interface The devices feature a 3-wire serial interface that directly connects to SPI, QSPI, and MICROWIRE devices without external logic. Figures 1 and 5 show the interface signals for a single conversion frame to achieve maximum throughput. The falling edge of CS defines the sampling instant. Once CS transitions low, the external clock signal (SCLK) controls the conversion. The conversion result appears at DOUT, MSB first, with a leading zero followed by the 12-bit, 10-bit, or 8-bit result. A 12-bit result is followed by two trailing zeros, a 10-bit result is followed by four trailing zeros, and an 8-bit result is followed by six trailing zeros. See Figures 1 and 5. The SAR core successively extracts binary-weighted bits in every clock cycle. The MSB appears on the data bus during the 2nd clock cycle with a delay outlined in the timing specifications. All extracted data bits appear successively on the data bus with the LSB appearing during the 13th/11th/9th clock cycle for 12-/10-/8-bit operation. The serial data stream of conversion bits is preceded by a leading "zero" and succeeded by trailing "zeros." The data output (DOUT) goes into a high-impedance state during the 16th clock cycle. The dual-channel devices feature a dedicated reference input (REF). The input signal range for AIN1/AIN2 is defined as 0V to VREF with respect to AGND. The single-channel devices use VDD as the reference. The input signal range of AIN is defined as 0V to VDD with respect to GND. These ADCs include a power-down feature allowing minimized power consumption at 2.5FA/ksps for lower SAMPLE SAMPLE CS SCLK DOUT 16 1 2 D9 0 HIGH IMPEDANCE 3 4 D8 5 D7 6 D6 7 D5 8 D4 9 D3 10 D2 11 D1 12 D0 13 0 14 0 15 0 16 1 0 HIGH IMPEDANCE SAMPLE SAMPLE CS SCLK DOUT 16 HIGH IMPEDANCE 1 2 0 3 D7 4 D6 5 D5 6 D4 7 D3 8 D2 9 D1 10 D0 11 0 12 0 13 0 14 0 15 0 Figure 5. 10-/8-Bit Timing Diagrams 20 16 0 HIGH IMPEDANCE 1 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs The source impedance of the external driving stage in conjunction with the sampling switch resistance affects the settling performance. The THD vs. Input Resistance graph in the Typical Operating Characteristics shows THD sensitivity as a function of the signal source impedance. Keep the source impedance at a minimum for high-dynamic-performance applications. Use a highperformance op amp such as the MAX4430 to drive the analog input, thereby decoupling the signal source and the ADC. Analog Input The devices produce a digital output that corresponds to the analog input voltage within the specified operating range of 0V to VREF for the dual-channel devices and 0V to VDD for the single-channel devices. While the ADC is in conversion mode, the sampling switch is open presenting a pin capacitance, CP (CP = 5pF), to the driving stage. See the Applications Information section for information on choosing an appropriate buffer for the ADC. Figure 6 shows an equivalent circuit for the analog input AIN (for single-channel devices) and AIN1/AIN2 (for dual-channel devices). Internal protection diodes D1/D2 confine the analog input voltage within the power rails (VDD, GND). The analog input voltage can swing from GND - 0.3V to VDD + 0.3V without damaging the device. ADC Transfer Function The output format is straight binary. The code transitions midway between successive integer LSB values such as 0.5 LSB, 1.5 LSB, etc. The LSB size for singlechannel devices is VDD/2n and for dual-channel devices is VREF/2n, where n is the resolution. The ideal transfer characteristic is shown in Figure 10. The electric load presented to the external stage driving the analog input varies depending on which mode the ADC is in: track mode vs. conversion mode. In track mode, the internal sampling capacitor CS (16pF) has to be charged through the resistor R (R = 50I) to the input voltage. For faithful sampling of the input, the capacitor voltage on CS has to settle to the required accuracy during the track time. VDD SWITCH CLOSED IN TRACK MODE SWITCH OPEN IN CONVERSION MODE D1 Normal Mode In normal mode, the devices are powered up at all times, thereby achieving their maximum throughput rates. Figure 7 shows the timing diagram of these devices in normal mode. The falling edge of CS samples the analog input signal, starts a conversion, and frames the serialdata transfer. CS R AIN1/AIN2 AIN CP Operating Modes The ICs offer two modes of operation: normal mode and power-down mode. The logic state of the CS signal during a conversion activates these modes. The powerdown mode can be used to optimize power dissipation with respect to sample rate. D2 Figure 6. Analog Input Circuit KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE CS SCLK DOUT 1 2 3 4 5 6 7 8 VALID DATA HIGH IMPEDANCE 9 10 11 12 13 14 15 16 HIGH IMPEDANCE Figure 7. Normal Mode ______________________________________________________________________________________21 MAX11661-MAX11666 To sustain the maximum sample rate, all devices have to be resampled immediately after the 16th clock cycle. For lower sample rates, the CS falling edge can be delayed leaving DOUT in a high-impedance condition. Pull CS high after the 10th SCLK falling edge (see the Operating Modes section). MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DOUT HIGH IMPEDANCE INVALID DATA INVALID DATA OR HIGH IMPEDANCE HIGH IMPEDANCE Figure 8. Entering Power-Down Mode CS 1 SCLK 2 3 4 DOUT 5 6 7 8 9 10 11 12 13 14 15 16 INVALID DATA (DUMMY CONVERSION) HIGH IMPEDANCE N 1 HIGH IMPEDANCE 2 3 4 5 6 7 8 9 10 11 12 VALID DATA 13 14 15 16 HIGH IMPEDANCE Figure 9. Exiting Power-Down Mode OUTPUT CODE However, pulling CS high before the 10th SCLK falling edge terminates the conversion, DOUT goes into highimpedance mode, and the device enters power-down mode. See Figure 8. FS - 1.5 x LSB 111...111 Power-Down Mode In power-down mode, all bias circuitry is shut down drawing typically only 1.3FA of leakage current. To save power, put the device in power-down mode between conversions. Using the power-down mode between conversions is ideal for saving power when sampling the analog input infrequently. 111...110 111...101 000...010 000...001 000...000 0 1 2 3 2n-2 2n-1 2n ANALOG INPUT (LSB) FULL SCALE (FS): AIN1/AIN2 = REF (TDFN, MAX) AIN = VDD (SOT23) n = RESOLUTION Figure 10. ADC Transfer Function To remain in normal mode, keep CS low until the falling edge of the 10th SCLK cycle. Pulling CS high after the 10th SCLK falling edge keeps the part in normal mode. Entering Power-Down Mode To enter power-down mode, drive CS high between the 2nd and 10th falling edges of SCLK (see Figure 8). By pulling CS high, the current conversion terminates and DOUT enters high impedance. Exiting Power-Down Mode To exit power-down mode, implement one dummy conversion by driving CS low for at least 10 clock cycles (see Figure 9). The data on DOUT is invalid during this dummy conversion. The first conversion following the dummy cycle contains a valid conversion result. The power-up time equals the duration of the dummy cycle, and is dependent on the clock frequency. The power-up time for 500ksps operation (8MHz SCLK) is 2Fs. 22 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs is never powered down. The user can also power down the ADC between conversions by using the power-down mode. Figure 12 shows for the 500ksps device that as the sample rate is reduced, the device remains in the power-down state longer and the average supply current (IVDD) drops accordingly. SUPPLY CURRENT vs. SAMPLING RATE SUPPLY CURRENT vs. SAMPLING RATE 2.0 1.5 VDD = 3V fSCLK = VARIABLE 16 CYCLES/CONVERSIONS 1.5 VDD = 3V fSCLK = 8MHz IVDD (mA) IVDD (mA) 1.0 1.0 0.5 0.5 0 0 0 100 200 300 400 500 SAMPLING RATE (ksps) Figure 11. Supply Current vs. Sample Rate (Normal Operating Mode) 0 20 40 60 80 100 120 140 160 SAMPLING RATE (ksps) Figure 12. Supply Current vs. Sample Rate (Device Powered Down Between Conversions) ______________________________________________________________________________________23 MAX11661-MAX11666 Supply Current vs. Sampling Rate For applications requiring lower throughput rates, the user can reduce the clock frequency (fSCLK) to lower the sample rate. Figure 11 shows the typical supply current (IVDD) as a function of sample rate (fS) for the 500ksps devices. The part operates in normal mode and MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs Applications Information Dual-Channel Operation The MAX11662/MAX11664/MAX11666 feature dual-input channels. These devices use a channel-select (CHSEL) input to select between analog input AIN1 (CHSEL = 0) or AIN2 (CHSEL = 1). As shown in Figure 13, the CHSEL signal is required to change between the 2nd and 12th clock cycle within a regular conversion to guarantee proper switching between channels. Layout, Grounding, and Bypassing For best performance, use PCBs with a solid ground plane. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the ADC package. Noise in the VDD power supply, OVDD, and REF affects the ADC's performance. Bypass the VDD, OVDD, and REF to ground with 0.1FF and 10FF bypass capacitors. Minimize capacitor lead and trace lengths for best supply-noise rejection. 14-Cycle Conversion Mode The ICs can operate with 14 cycles per conversion. Figure 14 shows the corresponding timing diagram. Observe that DOUT does not go into high-impedance mode. Also, observe that tACQ needs to be sufficiently long to guarantee proper settling of the analog input voltage. See the Electrical Characteristics table for tACQ requirements and the Analog Input section for a description of the analog inputs. Choosing an Input Amplifier It is important to match the settling time of the input amplifier to the acquisition time of the ADC. The conversion results are accurate when the ADC samples the input signal for an interval longer than the input signal's worst-case settling time. By definition, settling time is the interval between the application of an input voltage step and the point at which the output signal reaches CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CHSEL DOUT DATA CHANNEL AIN1 DATA CHANNEL AIN2 Figure 13. Channel Select Timing Diagram SAMPLE SAMPLE CS SCLK DOUT 1 2 0 3 D11 4 D10 5 D9 6 D8 7 D7 8 D6 9 D5 10 D4 11 D3 12 D2 13 D1 (MSB) 14 D0 0 tACQ 1/fSAMPLE tCONVERT Figure 14. 14-Clock Cycle Operation 24 1 0 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs Figure 15 shows a typical application circuit. The MAX4430, offering a settling time of 37ns at 16 bits, is an excellent choice for this application. See the THD vs. Input Resistance graph in the Typical Operating Characteristics. Choosing a Reference For devices using an external reference, the choice of the reference determines the output accuracy of the ADC. An ideal voltage reference provides a perfect initial accuracy and maintains the reference voltage independent of changes in load current, temperature, and time. Considerations in selecting a reference include initial voltage accuracy, temperature drift, current source, sink capability, quiescent current, and noise. Figure 15 shows a typical application circuit using the MAX6126 to provide the reference voltage. The MAX6033 and MAX6043 are also excellent choices. +5V 10F 0.1F VOVDD 3V 100pF C0G VDD 500I AIN1 500I 0.1F AIN1 470pF C0G CAPACITOR -5V 3 0.1F 2 MAX11662 MAX11664 MAX11666 AIN2 0.1F 470pF C0G CAPACITOR 10F 0.1F 4 5 10I 1 MAX4430 VDC SS CPU +5V 6 500I 4 MISO EP 7 AIN2 DOUT 10F 100pF C0G 500I SCK CHSEL 10F 0.1F SCLK CS REF +5V 10F AGND 10I 1 MAX4430 VDC 10F 5 4 OVDD 3 OUTF IN 2 1F OUTS MAX6126 GNDS GND NR 0.1F 1 0.1F -5V 3 2 0.1F 10F Figure 15. Typical Application Circuit ______________________________________________________________________________________25 MAX11661-MAX11666 and stays within a given error band centered on the resulting steady-state amplifier output level. The ADC input sampling capacitor charges during the sampling cycle, referred to as the acquisition period. During this acquisition period, the settling time is affected by the input resistance and the input sampling capacitance. This error can be estimated by looking at the settling of an RC time constant using the input capacitance and the source impedance over the acquisition time period. MAX11661-MAX11666 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. For these devices, the straight line is a line drawn between the end points of the transfer function after offset and gain errors are nulled. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of 1 LSB or less guarantees no missing codes and a monotonic transfer function. Offset Error The deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. Gain Error The deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal after adjusting for the offset error, that is, VREF - 1.5 LSB. Signal-to-Noise Ratio and Distortion (SINAD) SINAD is a dynamic figure of merit that indicates the converter's noise and distortion performance. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset: . SIGNAL RMS SINAD(dB) = 20 x log NOISE + DISTORTION) RMS ( Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: V 2 + V32 + V42 + V52 THD = 20 x log 2 V1 Aperture Jitter where V1 is the fundamental amplitude and V2-V5 are the amplitudes of the 2nd- through 5th-order harmonics. Aperture Delay SFDR is a dynamic figure of merit that indicates the lowest usable input signal amplitude. SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR is specified in decibels with respect to the carrier (dBc). Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture delay (tAD) is the time between the falling edge of sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio (SNR) SNR is a dynamic figure of merit that indicates the converter's noise performance. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR (dB) (MAX) = (6.02 x N + 1.76) (dB) In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade SNR. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. Spurious-Free Dynamic Range (SFDR) Full-Power Bandwidth Full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3dB for a full-scale input. Full-Linear Bandwidth Full-linear bandwidth is the frequency at which the signal-to-noise ratio and distortion (SINAD) is equal to a specified value. Intermodulation Distortion Any device with nonlinearities creates distortion products when two sine waves at two different frequencies (f1 and f2) are applied into the device. Intermodulation distortion (IMD) is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -6dBFS. 26 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs PROCESS: CMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 10 MAX U10E+3 21-0109 90-0148 6 SOT23 U6+1 21-0058 90-0175 ______________________________________________________________________________________27 MAX11661-MAX11666 Chip Information 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs MAX11661-MAX11666 Revision History REVISION NUMBER REVISION DATE 0 11/10 Initial release 1 1/11 Released the MAX11663 and updated Figures 11 and 12. 1, 23 2 6/11 Released the MAX11662/MAX11664/MAX11666. Updated the Electrical Characteristics. 1-14 3 11/11 Updated the Electrical Characteristics, Figures 13 and 15. 4 1/12 Updated Ordering Information. 1 5 4/12 Corrected the Aperture Delay in the Electrical Characteristics 3 DESCRIPTION PAGES CHANGED -- 4, 5, 6, 8, 10, 12, 14, 24, 25 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 28 (c) Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.